Introduction

"If you wish to make an apple pie from scratch, you must first invent the universe." — Carl Sagan, Cosmos

The tower of trust

Between "my program ran correctly" and "electrons obey Maxwell's equations" stands a tower of trust: the instruction set means what its manual says; the processor implements the instruction set; the netlist computes what the RTL describes; the digital story the netlist tells is what the analog circuit actually settles to; the circuit is what the geometry realises; the geometry is what the fab printed; and the transistors do what the device models claim. Every program run in history has silently relied on every storey at once. Industrial practice verifies one or two of them and takes the rest on faith — reasonably, because the faith is grounded in decades of engineering discipline and billions of working chips, but the faith is unaudited: no one has ever written down, in one place, what exactly is being assumed at each storey and how the storeys compose.

This book is a scoping study for auditing all of it. The question it maps: what would it take to produce a machine-checked proof that one specific, physical, fabricable chip runs its programs correctly — starting from field equations over the silicon and ending at the instruction set? Not a chip designed to be verifiable, but a mainstream design produced by the ecosystem's own tools; not an idealised model of it, but the concrete artifacts the flow emits, distortions and datasheets and all.

It is not the proof. Carrying the proof out is a decade-scale project for a small group; the deliverable here is the map — for each layer of the tower, what the theorem is, how it would be proved, what it rests on, and what is genuinely unknown. The organising principle, adopted from the start: assume unbounded proof capacity, so that everything merely hard collapses to time. What survives that collapse — the claims no proof can reach, because they are empirical, or legislative, or genuinely probabilistic — is the result. The axiom register is the book's primary deliverable, and the six layer studies exist to justify its rows.

How correctness is established today

To see what is new here, it helps to know what the industry actually does — which is more, and less, than outsiders expect.

The overwhelming bulk of design verification is simulation: testbenches driving the RTL through billions of pseudorandom, coverage-steered cycles on server farms, with emulation hardware for the workloads simulation can't reach. It finds bugs with great efficiency and proves nothing. Formal methods entered the mainstream through a famous accident: the 1994 Pentium FDIV bug — missing entries in a division lookup table that shipped in silicon, cost Intel a $475M recall, and convinced the microprocessor industry that some properties are worth proving. The years after produced the field's industrial successes: floating-point units verified by theorem proving (AMD's division microcode in ACL2; Intel's FP algorithms in HOL Light), model checking — exhaustive state-space analysis of finite systems, the technique behind the 2007 Turing Award to Clarke, Emerson, and Sifakis — applied to protocols and control logic, and two formal-flavoured checks that became routine sign-off for every chip: equivalence checking, which proves the synthesised netlist matches the RTL, and static timing analysis, which covers all timing paths by construction. Below the netlist, no one proves anything: the geometric and physical storeys are governed by design-rule checking, layout-versus-schematic comparison, and manufacturing test — engineering disciplines with excellent track records and no theorems.

Academia has periodically tried to go end to end, and the history is instructive. The Viper microprocessor (UK Royal Signals and Radar Establishment, late 1980s) was fabricated and marketed for safety-critical use on the strength of a "proven correct" claim — and became the field's cautionary tale when Avra Cohn, who built the machine-checked proofs, published the sharpest analysis ever written of what such a claim can mean: the proofs related two formal models, neither of which was the physical chip; the verification was never completed down to the gates; and the storeys between the models and the silicon were exactly as unproved as anyone else's. Warren Hunt's FM8501 and FM9001 (1980s–90s, in the Boyer–Moore prover) verified real processor designs down to the netlist level — FM9001 was fabricated; the CLI verified stack (1989) composed a verified assembler, compiler, and processor into the first multi-storey artifact; Anthony Fox verified the ARM6 microarchitecture against the ARM ISA in HOL (the closest ancestor of this book's L3); the German Verisoft project (2003–07) verified the VAMP processor from ISA to gate level and built a verified software stack above it. More recently, the CakeML project's verified compiler runs on Silver, a processor verified in HOL4 down to its Verilog implementation and run on an FPGA — the vendor's Verilog-to-bitstream synthesis being the remaining trusted step — and Claire Wolf's riscv-formal brought bounded model checking to open-source RISC-V cores as an engineering practice. On the software side, CompCert and seL4 demonstrated that realistic compilers and OS kernels can be verified — and their experience with what a verification is conditional on shaped this book's ledger discipline.

Every one of these efforts stops at a storey boundary — the netlist, or an idealised gate-level model — and hands the rest to the fab's engineering. That is the gap this study is about: not any single storey, most of which have at least been attempted, but the composed statement about a physical object, with the physical storeys as theorems-with-hypotheses rather than background faith, and every surviving assumption in one auditable list. To our knowledge no one has stated that theorem before, let alone proved it.

The plan

The stance throughout is validation of an existing design, not design of a new one. The SoC at the centre was designed and is maintained by others — it is the mainstream of open hardware research, engineered to the ecosystem's best practices — and the job is to check that those practices delivered, not to re-engineer the artifact. This inverts the usual verified-hardware methodology — design for verifiability, then prove — and the inversion is the point: a theorem about a design anyone can regenerate, harden, and have fabricated says something a theorem about a bespoke academic core does not. Where a tool or an artifact cuts a corner, the finding is recorded (the register already holds several: two independent DRC engines return different verdicts on the same layout; a signoff step exhausts memory instead of reporting) and, if necessary, a minimal modification is priced. The proof architecture assumed is a hybrid one: a proof assistant hosting the statements and the glue, with untrusted industrial-strength tools — SAT solvers, synthesis tools, timing engines — admitted only through certificates their runs emit and small verified checkers replay. No tool is trusted; every tool is used.

One consequence of the stance is a rule about era: every artifact in the tower — RTL, netlist, constraints, layout, timing reports — is produced by one pinned flow, run by us, from sources we can modify. Nothing is inherited from a build that cannot be re-executed. The endgame of the study is tools that emit certificates as they run, and that requires tools that can be patched — which the layers below repeatedly cash in.

The target

The study is grounded in one artifact stack, chosen because it is the rare intersection of fully open and physically realisable. In 2020, Google and SkyWater Technology (a foundry in Bloomington, Minnesota, operating a former Cypress fab) released the SKY130 process design kit as open source — the first time the full design-side collateral of a commercial 130 nm process (design rules, device models, standard cells; the fabrication recipe itself stays in the foundry) was public. It remains the floor for open processes: no smaller node has an open PDK, so "modern" in this book means modern architecture and toolchain, never modern frequency. Merchant multi-project-wafer shuttles run against SKY130 continuously; the deliverable they accept is exactly the GDSII this book's flow emits, so the physical object at the bottom of the tower is a purchase order away rather than a hypothetical.

The design side sits on the stack that open hardware research has consolidated around. Chipyard (UC Berkeley) is the SoC framework: it composes a system — core, caches, interconnect, peripherals, debug — from parameterised generators written in Chisel, a Scala-embedded hardware language. Elaboration produces FIRRTL, an intermediate representation with a written specification, and CIRCT — the LLVM/MLIR hardware compiler — lowers it to SystemVerilog. The physical flow is Hammer, Chipyard's tool-abstraction layer, driving Yosys for synthesis and OpenROAD (a DARPA-funded academic effort) for place-and-route, with the venerable Magic layout editor — begun at Berkeley in the 1980s and still maintained — KLayout, and Netgen for the geometric and connectivity checks. On-chip memories come from SRAM22, an open SRAM generator for SKY130. Every input is pinned by commit and checksum; every artifact this book measures (RTL, netlist, GDS geometry, timing reports, constraint files) is regenerated by the flow in this repository.

The processor at the centre is Rocket — the original RISC-V implementation, begun at Berkeley alongside the ISA itself, the lineage core of the ecosystem (commercial RISC-V cores descend from it, and it has been fabricated dozens of times). The configuration is Chipyard's TinyRocketConfig, and the target follows the generated artifact exactly: a single 5-stage in-order RV32IMAC core with machine and user modes, physical memory protection, a 4 KiB instruction cache, a 16 KiB tightly-integrated data memory, a TileLink interconnect, a standard RISC-V debug module reached over JTAG, a CLINT and PLIC for interrupts, and a UART — with off-chip access carried by a serialised TileLink port at the pads. Simplicity is not the goal, realism is. The costs are recorded where they bite — machine-emitted SystemVerilog from a three-stage compiler pipeline, a pipeline and a cache in the refinement proof, generators whose semantics live in their implementation — and the study prices them rather than designing them away.

RISC-V, briefly

RISC-V is an open instruction-set architecture begun in 2010 at UC Berkeley (Krste Asanović, Yunsup Lee, Andrew Waterman, with David Patterson) — the fifth in the Berkeley RISC lineage that started with Patterson's RISC-I in 1981 and gave the reduced-instruction-set idea its name. Unlike x86 or ARM, the specification is freely implementable by anyone: stewardship passed to a foundation in 2015, now RISC-V International, and an ecosystem of open implementations grew around it — the ecosystem this book's processor comes from. Two features matter specifically for this project. The ISA is modular — a small base plus optional lettered extensions — so a small core can implement an honest subset rather than an apologetic fraction. And the standard did something this book leans on directly: RISC-V International adopted a machine-readable, executable formal specification (in Sail, a language purpose-built for ISA semantics) as its official golden model, which new extensions are required to extend as part of ratification. The spec this book verifies against is therefore not a private reconstruction from an English manual; it is the standard's own formal artifact, imported.

The six layers

The tower is cut into six layers. Each names an object — the abstraction at that altitude — and carries, as one of its subsections, the theorem that connects it to the layer above. Numbered by artifact altitude from physics up; bottom-up, since that is how the trust composes:

• L0 — physics. The device and field: from field equations and fitted transistor models to the electrical behaviour of the wires and transistors. Also the error model — what survives as genuine probability (particle strikes; almost nothing else). This is the one layer that carries ε; everything above it is deterministic.
• L1 — the electrical layer. The circuit as a space of transfer functions under a constraint system (this is where the old geometry and timing concerns merge). Two theorems live here: the drawn polygons, distorted within tolerances, still realise exactly the intended netlist with certified parasitics; and — the edge upward — timing closure, the combinatorial geometry/interference checks, and gain-based restoration together turn those transfer functions into a discrete synchronous machine (the bridge theorem everyone relies on and no one has stated). The layer trades ε for a constraint system.
• L2 — logic. The synchronous machine: flops plus combinational logic over a Boolean vector. Its edge upward is an equivalence, not an abstraction step — the hardened netlist and the source RTL denote the same machine, at gate and word granularity, by certificates rather than trust.
• L3 — RTL and microarchitecture. What the emitted SystemVerilog means: a formal semantics for the subset the design occupies (the same machine, word-level), and its edge upward — the theorem a computer architect would recognise, that the hardware refines the instruction set. The tower's irreducible proof.
• L4 — the ISA. The specification itself: the imported Sail standard, plus the parts that exist only as informal prose and must be formalised.
• L5 — the system. What the end-to-end claim is even about: the chip's observable behaviour at its pads, with the memory map, peripherals, and power in the specification where they belong.

Each layer names an object and, in one subsection, proves the theorem linking it upward; the layers compose along those seams into the top-level statement — the next chapter displays the whole chain. Two of those links are conditional on probabilistic events (a particle strike, an unresolved synchroniser), and those two conditions are exactly where the theorem's ε lives; everything else is deterministic. The book's chapters run top-down, L5 to L0, because the material gets progressively crunchier as you descend — and because reading the claim before its foundations mirrors how the trust is actually spent.

The overview that follows is the mathematical front door: the top-level statement, the objects at the seams, the dispatch of the proof into layers, and their prices. The appendices hold the ledgers — axioms, findings, the glossary, a reading list, and the bibliography. Everything else is the six layers.

Overview — the mathematical content

Background

The introduction set the scene — the tower of trust, how the industry establishes correctness today, the validation-not-design plan, the Chipyard/Rocket target, and the six layers in prose. This page is the mathematical front door: the statement the project is trying to establish, the named objects at the layer seams, and the dispatch of the proof into layers with their prices. Project structure and tooling live in the repository's root README; the flow's jargon is in the glossary, and textbook on-ramps for the fields the tower spans are in the reading list.

The top-level statement

Let d be a fabricated die, F a program image, E an environment (supply, clock, temperature, radiation, asynchronous inputs). Write obs(d,F,E) for the observable trace at the pads and Sys(F) for the pad-trace semantics of the system specification — both defined by L5, not primitive. (How F gets into the machine — resident boot ROM, the debug module, or the serial TileLink port — is part of L5's boundary decision, not an aside: every load path is a pad-trace prefix.)

     Envelope(d, E)                                     ← L0/04, V1–V7
  ∧  Axioms                                             ← axioms.md
  ⟹  P[ obs(d,F,E) ⊑ Sys(F) ]  ≥  1 − ε(T)

      ε(T)  =  λ·A·T·AVF          particle strikes         (P2)
            +  N_sync·P_meta(T)   unresolved synchronisers (P1)
            +  P_droop            supply excursions        (P6)

(Symbols: λ is the particle flux and A the die area; AVF, the architectural vulnerability factor, is the fraction of raw bit-flips that matter architecturally; N_sync counts the synchroniser boundaries where the design meets unclocked inputs. All three ε-terms are derived, not decorative — each has its own chapter.)

Three features of this statement are deliberate and worth defending.

It is probabilistic, and irreducibly so. No amount of proof removes ε. P1 is irreducible by Marino's theorem — no continuous bistable escapes unbounded settling — and P2 is a Poisson process driven by an external flux. What proof can do is derive their coefficients rather than measure them, which is what shrinks P1 and P2 in the axiom register without eliminating them.

Both ends are slots filled by their own layers, and neither is a placeholder for something easy. Envelope is L0's, and is a genuine intersection of five structurally different constraint shapes (L0/04). Sys is L5's, its ISA core is L4's — which for the Rocket core must include the machine-mode privileged subset (CSRs, traps, interrupts, PMP) alongside the base ISA — and parts of the surrounding SoC's behaviour exist only as generated code, device-tree annotations, and de-facto register conventions, so the residual device/CSR semantics must be authored rather than imported (L4, L5).

⊑ is trace refinement up to stuttering, not equality. The implementation takes many cycles per architectural step; L3's obligation is a stuttering simulation with a measure function, not a cycle-accurate correspondence.

The spec tower

The named objects at the seams. Each is the node of some layer — the object that layer is. Every layer README opens with its node (the object) and its edge up (the theorem carrying that object to the next one): a node supplies an object; the edge above it is a theorem connecting two objects.

One identification is used silently everywhere and stated only here: N is a single shared object. The netlist that L1's LVS certifies the geometry against, the netlist L1's STA runs on, and the left-hand side of L2's equivalence are all ⟦ChipTop.mapped.v⟧ — the flow's hardened netlist — under one parse. X1's obligation, one parser, three consumers.

The organising principle

With unbounded proof capacity, the deliverable is the axiom list.

Everything merely hard collapses to time. What survives is what is not a theorem: specification fidelity, empirical models, physical facts, and genuinely probabilistic phenomena. So each layer is organised around what it discharges and what it introduces, and the running register is axioms.md — with the open mathematical questions (M1–M8) kept separate from the axioms, because effort could in principle remove them.

Notation. Lettered identifiers index the appendix registers: S/E/P/X+number are axioms, F+number are findings about the design and its flow (unestablished or false hypotheses), M+number are the open mathematical questions — all in Axioms. Layer-local check families are defined in their owning chapters: W1–W4 (netlist well-formedness, L2/01), G1–G6 (geometric checks, L1/12), V1–V8 (the operating envelope, L0/04), C1–C7 (spec choices, L4/02), B1–B3 (claim boundaries, L5/01). The spec-tower objects are introduced just below; the standalone value X — the untracked third logic value — is in the glossary. Reading top-down, these appear before their definitions; every mention is a link.

Backgrounds. No single reader arrives knowing all of the fields this book crosses — the required intersection (computer architecture ∩ EDA ∩ analog design ∩ device physics ∩ PDE theory ∩ formal methods) is empty. So every chapter after the introduction (which is background throughout) opens with a Background section written for a reader from outside its field: the concepts, mechanisms, and proof techniques the chapter is about to use, explained from scratch (the layer chapters' are brief orientations; the sub-chapters' do the real teaching). Experts in a chapter's home field should skip its Background; everyone else should not. The glossary is the quick-lookup complement; the reading list is the textbook-depth one.

The dispatch

Each layer's named obligations. This is the proof skeleton; the layer documents are the expansions.

Every layer is a node — an object at one abstraction altitude — and the theorem connecting it to the layer above is one subsection of it, its "edge up." Definitions live in nodes; theorems live between them, on the edges. The tower has six nodes (L0–L5) and five edges. Two of those edges are decisive crossings: the ε-crossing (L0→L1), where physics establishes the deterministic EE abstraction, and the digital crossing (L1→L2), where timing closure, the geometry/interference checks, and gain-driven restoration turn analog transfer functions into a Boolean machine. Below the ε-crossing the world is analog and probabilistic; between the two crossings it is deterministic-analog; above the digital crossing it is Boolean and architectural.

Nodes and edges fail differently, and the asymmetry is why they are marked. A wrong edge (theorem) will not prove — the kernel guards it. A wrong node (definition) yields a true theorem about the wrong object — only adequacy guards it, which is why the definition nodes (L4, L5, and the L3 node) carry adequacy machinery instead of proofs. Most crossing-constraints are discharged — established at the edge and then gone (timing, restoration, the interference budgets). One survives as a standing hypothesis of the node above: well-formedness (acyclic combinational logic, no shorts, no runaway) cannot be spent at the digital crossing, because L2's Boolean machine is only well-defined under it (W1–W4). (The table runs bottom-up, L0→L5, following the composition; the book's chapters run top-down, L5→L0 — start wherever suits.)

The effort accounting. Figures are for one competent person and are the sums of the subcomponent estimates — the two merged nodes (L1 = geometry + timing, L3 = RTL semantics + the refinement) show their two summands. The original per-layer figures — seeded before the decomposition at "a few years each" — ran roughly 2× higher; scoping the pieces is precisely what revised them, and the sums reflect the better understanding, so they replaced the anchors. One cross-cutting cost is priced separately because no layer owns it: shared infrastructure — the hybrid proof framework itself, bitvector automation, symbolic simulation, and the LRAT/PAC checker integrations — 1–2 person-years, consumed by every theorem edge. Naive sequential total: 8–15 person-years, before the FPGA alternative (which deletes L1's geometry half, 2–4 of them).

Note one deliberate inversion: L2's CEC edge consumes L3's object ⟦RTL⟧, so proof order is not tower order. The numbering is by artifact altitude — netlist below RTL — not by logical dependency.

How they compose

Each ≔ line is a node (an object supplied); each ⊨ line is that node's edge up (a theorem to the next object). ≔/⊨ alternate all the way up.

device d ∈ Envelope
  ≔ L0    Field(d), device models, ε                 [the physics node; E1, Poisson error model]
  ⊨ L0→L1 Field(d) ⊑ Contracts(N)                    [electrical abstraction; M3, M7; modulo E1]  † ε-crossing
  ≔ L1    N and RC well-defined ∀A in the E7 family  [the EE-circuit node; (H1)(H2) checked, E7 ⊨ (H3); M2]
  ⊨ L1→L2 Contracts(N) ⊑ Mealy(N)                    [digital crossing = timing+geometry+restoration; M5; F-series] †
  ≔ L2    Mealy(N)                                   [the synchronous machine; W1–W4 standing]
  ⊨ L2→L3 Mealy(N) ≈ρ ⟦RTL⟧                          [the CEC — horizontal equivalence; ρ = F5]
  ≔ L3    ⟦RTL⟧ = the microarchitecture              [measured census]
  ⊨ L3→L4 ⟦RTL⟧ ⊑ ISA                                [the invariant — the genuine abstraction step]
  ≔ L4    ISA  = Sail-RV32 ⊕ machine-mode subset      [S2, S3, S4]
  ≔ L5    Sys(F) = ISA ⊕ memory map ⊕ devices        [X4, bus contract — the ISA⊕devices composition]
  ────────────────────────────────────────────────────────
       obs(d,F,E) ⊑ Sys(F)   with probability ≥ 1 − ε(T)

† is where ε enters. The two marked lines hold on the event "no particle strike (P2) and no unresolved synchroniser read (P1) during [0,T]"; every line above them is deterministic conditional on that event, and ε(T) is exactly the probability of its complement (plus P6's droop term). The probability in the conclusion is not smeared across the chain — it is the measure of the conditioning event for two specific lines.

Interfaces

Each node exports a thin object, and each edge is one arrow up. The functional chain (L2→L5) and the physical chain (L0→L2, the two crossings) are nearly independent and meet only at the netlist:

                    L5  Sys(F): pad traces (memory map, serial TL, UART, obs)   ← top node
                     ↑  ISA ⊕ devices ⟹ Sys — composition at the chosen boundary
                    L4  ISA (Sail + the Rocket-specific parts authored)          ← definition node
                     ↑  the invariant — stuttering refinement, word-level        ← THE WORK
                    L3  ⟦RTL⟧ = the microarchitecture (buses, arithmetic intact) ← definition node
                     ↑  the CEC — horizontal equivalence, certificates
                    L2  the synchronous machine / gate netlist  ←── meeting point ───┐
                     ↑  DIGITAL CROSSING: timing + geometry checks + restoration     │ annotations
                    L1  the EE circuit: extraction ⟹ N + RC, timed contracts, SDC    │ (delay, RC)
                     ↑  ε-CROSSING: field sim ⟹ deterministic transfer functions     │
                    L0  devices/field: cells ⟹ Boolean functions, ε ────────────────┘

The refinement proof never touches RC. Electrical data exists solely to discharge the digital crossing's hypotheses. That is the cleanest seam in the stack and should be preserved deliberately — see L1 on keeping crosstalk out of the interface, and treating any net that would need a functional coupling constraint as a layout bug.

Note that geometry is not a layer — it splits by character. The continuous, field geometry (transistor and wire shapes, RC) lives in L0's edge up, the ε-crossing, where the field simulation runs on it to establish the transfer functions; it is analog. The combinatorial, relational geometry (tap density, min spacing, "≥ N apart" checks) lives in L1's edge up, the digital crossing, where each check discharges a budget L0 set — L0 states an analog budget ("interference < X ⟹ ε bounded"), and the layout check is the finite combinatorial proof the budget holds. So a safety condition is stated in one layer and discharged in another: L0/06 carries the dispatch table, and L0 owns the statement of every envelope condition but the check for only one.

The composition, machine-checked — and its seam ledger

The chain above is not only prose: it is a Lean theorem, chip_realises_isa (dieBeh = isaBeh), which says the physical die and the ISA reference produce the same pad-trace on every program, and it type-checks — the layer boundaries genuinely line up. Its content is entirely in what it assumes, and #print axioms reads that back exactly. One boundary is a real, sorry-free proof: the netlist ↔ RTL middle (trace_refines, composing the proved one-step l2_commutes across cycles). Every other arrow in the diagram is a named interface axiom, because the layers that would discharge it are still proof-phase.

Those interface axioms are the honest measure of "the layers connect formally": each is a seam the thesis claims but has not yet proved. They are the arrows of the diagram, and — this is the gap the Lean attempt surfaced — the per-layer scoreboards scored the layers' internal obligations but never scored the seams. So the seams are now a first-class section of the scoreboard (IF/*, generated by tools/check-interfaces.py), one row per arrow, and are described in full in the seams appendix: the M5 timing bridge (iface_L1_timing), extraction+grounding (iface_L1_L0, which composes the celltopo/routecheck/LVS islands nothing else joins), the RTL front-end (frontEndCommutes), matched reset (reset_corr), the L3 refinement invariant (iface_L3), and the ISA/system boundary (iface_L4_L5) — plus the one dischargeable trust anchor the equivalence certificates rest on (miterCNF_sound). Closing the tower is discharging those seven rows; until then, the end-to-end theorem is real but conditional, and says precisely on what.

Three structural facts that recur at every layer

These are why the edifice is possible, and they shape every proof in it.

1. Nothing accumulates. Every layer has a mechanism that resets the error budget: gate restoration kills noise accumulation across logic depth; the clock edge kills timing-error accumulation across cycles; local variation adds in quadrature (√n) rather than linearly along a path; ECC plus scrubbing converts a linear-in-time failure rate into a quadratic one. Consequently every proof here is inductive with a fixed invariant, never one tracking a growing quantity.

2. Continuous perturbations get discharged; discrete events get carried. The continuous mechanisms are suppressed by hundreds of orders of magnitude — thermal escape faces a ~7,500 kT barrier, giving ~10⁻³²⁸⁵ — and should be bounded away and deleted, not carried as epsilons. The discrete ones (particle strikes, manufacturing defects) are Poisson, do not shrink with margin, and are handled by redundancy or by test, never by better analysis. Confusing the two is the most common modelling error in this area, and the trap is that coupling capacitance looks like the first kind and behaves like the second: it is additive, so its far-field sum needs a genuine convergence argument (M2) rather than a smallness claim.

3. Amortisation is the whole game. The ~400 standard cells of the library, verified once, cover every design on the process — this design's hardened netlist draws its 51,359 instances from just 96 cell types. One SRAM macro proof covers every instance of that macro (the 2 KiB data array appears twice; the memory obligation is parametric in depth, so size costs area, never proof). And because the design is generated, its entropy is the configuration: a few dozen lines of Scala elaborate to 228 modules and 9.4 MB of SystemVerilog. The per-design content is far smaller than the artifact size suggests.

A pattern worth naming

Recurring often enough to be a heuristic rather than a coincidence:

A real physical instability, prevented by a design rule, which is therefore secretly a hypothesis of a well-posedness or boundedness claim rather than a manufacturing constraint.

Instances so far: min-width and min-spacing are the hypotheses of L1's topology-preservation theorem; tap coverage is what destroys latch-up's second PDE solution branch (M1), i.e. what makes "the transistor's I-V characteristic" well-defined; the voltage rating keeps impact-ionisation terms out of the model and hence keeps global existence available; tied metal fill is a precondition of M2's cascade, since floating conductors relay rather than screen.

Several DRC rules are the side conditions of theorems nobody has written, and recovering those theorems may be the cleanest way to say what a rule deck actually means.

The certificate archetypes

Every PASS obligation on the scoreboard is discharged the same way — a tool emits a witness an independent checker re-verifies — but the checkers are not equally trustworthy, and the ladder is worth naming. Ordered by distance to a self-checking proof:

1. Functional, re-checkable. The tool's output is verified over the full input space by a second, simpler program. celltopo derives a cell's switch-level Boolean function from its transistors and checks it equals the Liberty function over the whole truth table; the CEC trail (L2/04) dumps each synthesis pass's miter and a SAT refutation an independent solver replays. The anchor is a single checker-soundness line (the truth-table comparator; the DRAT checker) — nothing else is trusted.

2. Independent witness. A structural property re-derived from scratch, independent of the tool that made the artifact. routecheck re-verifies the router's no-opens/no-shorts from the routed DEF by union-find and a sweep-line — trusting the witness algorithm, not the router.

3. Conservative bound over a trusted model. A monotone or interval argument that a specification number bounds a physical measurement. spicecheck screens each Liberty delay against an ngspice/BSIM4 simulation; the power-grid droop check reduces to a box-corner evaluation because the grid Laplacian is an M-matrix (monotone). Here a physical model (BSIM4, the Laplacian) enters the trust base, discharged only up to the model's fidelity.

4. Oracle against a golden model. An execution checked instruction-by-instruction against a reference. cosim runs the hardened RTL against spike and confirms every committed instruction's PC, writeback, and CSR. The golden model is trusted; this is the executable precursor to the L3 refinement proof, not a substitute for it.

5. Structural census. A finite decidable predicate re-run over the artifact — W1–W4 on the netlist, the memory-map / boundary / interrupt checks against the device tree, the RTL construct census. The predicate itself is small and auditable; that is the whole trust.

The ladder is exactly where the remaining trust concentrates: (1)–(2) hand back something independently verifiable, while (3) rests on a physics model and (4) on a reference implementation — which is why the analog models and the ISA oracle sit next to the axiom register's EXTERN entries. The taxonomy is made precise in the project's Lean skeleton (lean/, Prelude/Certificates), where each archetype is a typed certificate whose soundness axiom is exactly its anchor, and every layer L0–L5 carries at least one certificate-backed, sorry-free leaf.

Status

Open mathematics (M1–M8 in axioms.md): M2 (the screening exponent) and M5 (the bridge theorem) are the two the project's structure most depends on; M1 (uniqueness for stationary drift–diffusion) is the only one that is open mathematics rather than open formalisation.

Established for this design — the parts that are not speculative:

• The full generation chain reproduces from pinned sources: Chisel elaboration through FIRRTL and CIRCT to SystemVerilog, synthesis to a netlist with zero unmapped cells, all memories resolved to three SRAM macro kinds. The artifacts the layers name exist and were produced here.
• Independent signoff engines are not interchangeable, and the register carries the measurement: on the same layout, one DRC engine reports clean while another reports violations — so a single engine's verdict is treated as one witness, and the geometric checks (G1–G6) are stated engine-independently.

Unestablished for this design (the F-series in axioms.md): the physical signoff — multi-corner timing, DRC, LVS on the final layout — is not yet closed by the flow, and until it is, the hypotheses of the bridge theorem are not established; the SDC exception set is unverified; register correspondence through synthesis is unknown. The checker suite that pins these rows is being re-anchored to the flow's artifacts, and the scoreboard tracks exactly which obligations have a running check.

See findings.md for the measured data behind all of it — and the scoreboard for the live checker verdicts of the commit this book was built from: every obligation as PASS, FINDING, TODO (with its blocker named), or EXTERN.

The chapters descend the tower from here: L5 first — the claim — down to L0, where it runs out of turtles.

The die explorer

Everything in this book is grounded in one physical artifact: the routed layout of the target chip. This page lets you look at it — the actual metal the detailed router placed, read straight from ChipTop.def and the cell GDS, rendered as vectors you can pan, zoom, and toggle.

↗ Open the explorer full-screen

What you're looking at, and where each layer proves it

The explorer is a zoom hierarchy, and each level is the subject of a layer of this book:

• The die — 3.59 × 2.99 mm, with the five SRAM macros (the caches) carved out as labelled boxes. The floorplan and the macro contracts are L2/02.
• The metal layers (met1–met5) — every wire the router placed, 559,285 segments. That two nets crossing on different layers don't connect, while same-layer overlap would be a short, is exactly the no-shorts half of the routing witness; the no-opens half is that each net's routing self-connects. Both are machine-checked — all 41,287 two-pin nets connect, zero shorts — by tools/routecheck.py.
• The vias — 554,469 of them, coloured by the layer pair they bridge (li1–met1 grey-blue, met1–met2 purple, up the stack). A via is the only place two layers connect; the grey-blue li1–met1 vias are where routing meets a cell pin — the pin geometry of L1/02.
• The cells — split into the 67,893 logic gates and flops and the 135,134 well-taps and fill. Taps carry no logic: they tie the wells to the rails to prevent latch-up (L0/06, the tap-coverage condition). Hover any cell to see what it is.
• The transistors — zoom past ~24 px/µm and the standard cells resolve into their real geometry: green diffusion, red poly gates (a gate crossing diffusion is a transistor), blue met1. This is the L0 device level — the bottom of the tower, where the digital abstraction meets the silicon. Every instance is one of only ~122 distinct cell layouts, drawn once and placed everywhere.

How it's built

tools/chipviz.py reads the routed DEF into a compact per-layer segment blob (gzipped uint16); tools/extract-cells.py pulls the ~122 used cell masters' polygons from the GDS with gdstk; tools/build-chipviz-html.py assembles a single self-contained page that decompresses the blobs in the browser (DecompressionStream) and draws them on a canvas with viewport culling — no rendered pixels served, resolution-independent at any zoom. It regenerates from the flow artifacts; see tools/build-book.sh.

L5 — The system specification

Node — the top of the tower: Sys(F) and obs, the two objects the overview's top-level statement quantifies over (00–05); Sys(F) = ISA ⊕ memory map ⊕ devices, with the ISA ⊕ devices ⟹ Sys composition — the edge into this node from L4 — carried by 03. No edge up: this is where the tower ends. A definition node — specification authoring, not proof. Consumes: ISA (L4), device datasheet models (X4).

Background

This is the first layer of the book and the top of the tower, and it answers a question that sounds administrative but is foundational: what is the end-to-end theorem about? Not the ISA — an instruction set has no pins, and no statement about it mentions a physical object. The only interface a chip has with the world is its pads, the few dozen metal contacts the package's pins bond to, so the top-level specification must be a set of allowed pad-signal histories, and everything standing between the processor core and the pads becomes spec rather than scenery: the memory map, the boot ROM and the serial TileLink port the program arrives by, the UART the output leaves by, the JTAG debug port, and the power supply's arrivals, sags, and departures.

The chapters build exactly that. 00 defines the two top-level objects; 01 decides which physical object the claim is about (core, SoC, or the device you can hold); 02 writes the promises core and fabric exchange; 03 models the peripherals; 04 handles power, including brown-out; 05 fences off the configurations the theorems don't cover. Each chapter's own Background introduces its protocols and mechanisms from scratch.

Statement

This layer owns the map from architecture to observable behaviour — Sys(F) = ISA ⊕ memory map ⊕ serial TileLink ⊕ UART ⊕ debug/boot machinery, rendered as timed pad traces, and obs as the physical observation (00). The boundary test with L4: move the core to an FPGA and L4 survives byte-for-byte while this layer is replaced wholesale — L5 is this chip.

Subcomponents

Interfaces

Consumes: ISA (L4), L3's configuration record, the SoC RTL and its generated device tree (as 03's raw material), X4's models per B-level. Exports: Sys(F) and obs to the overview; the bus contract and B to L3; the configuration objects to the operating-conditions clause; the epoch requirements to the board (supervisor, sequencing).

Axioms introduced

X4 (device datasheet models) — a scoping dial, not a monolith: B1 needs none, B2 the on-die batch, B3 all of it, including whatever agent sits across the serial TileLink port; each theorem conditional on exactly its batch (01).

The layer's shape

Two definitions and four consequences. 00 fixes the objects, with the alphabet choice forced from below (epochs need prefix closure, which only the physical level has). 01 fixes what the claim is about, in three widening rings. The remaining files are the composition's components: the interface half (02), the address-and-device half (03), time's outer structure (04), and the domain clause (05). The recurring find of the layer: the SoC's small control devices keep receiving their formal jobs here — the boot-address register (boot promise), the tile-reset setter (epoch structure), the clock gater (operating-conditions knob), the error device (the bus contract's failure clause) — continuing the pattern that nothing in this design is decorative.

Open problems

1. Author the bus contract (02) — gates L3's refinement statement; days.
2. The RTL-vs-generated-metadata diffs (03) — drift between RTL, device tree, and register maps is the expected finding.
3. The UART framing-error decision and the rest of 00's derivation stack.
4. The F-immutability check and the supervisor inequalities (04).
5. Whether the pad ring and the serial-TileLink far end get behavioural models (B3) or the claim stops at B2 (01).

First experiments

• Write the B1 bus contract and check it against the tile's TileLink transactions in simulation (02) — unblocks L3.
• Extract the memory map from the RTL, diff against the generated device tree and register maps (03).
• State B3 for one hello-world image — "with F = this image in the boot path, the UART emits 'hello' at the configured baud" — fully formally, even unproven: it exercises every definition in the layer and will surface each one that is missing (01).

Effort

~6 months, definitional. The risk profile matches L4: errors here are invisible to every layer below and produce a true theorem about the wrong system.

Reading

The TileLink specification — the protocol 02's contract restricts. The RISC-V debug specification (the JTAG port is a pad-visible agent with its own protocol). The generated device tree and register maps — 03's provenance table maps them.

L5/00 — Sys(F) and obs: the two definitions

Background

A specification, in the sense used throughout this book, is a set of allowed behaviours, and a behaviour is a trace: a sequence of observations over time. To specify a machine you must therefore first answer a question that sounds trivial and is not: observations of what? A program's variables are not observable — they are an abstraction maintained by the processor. The processor's registers are not observable either — they are voltages on wires buried under many layers of metal. The only physical interface a chip has is its pads: the few dozen metal contacts around the die's edge that the package's pins bond to. Everything the chip will ever do to the world, it does by moving pad voltages; everything the world does to the chip arrives the same way. So the top-level specification must ultimately be a set of allowed pad-voltage histories, and this chapter defines both sides of that statement: Sys(F), the allowed set, and obs, the function that turns a physical run of the die into a trace that can be compared against it.

To see what has to go into Sys, look at what surrounds the processor core. This chip has no screen or keyboard; it talks to the world through a handful of serial interfaces, each of which is a small machine in its own right. Bulk data crosses the boundary over the serial TileLink port: on-chip bus transactions are cut into 32-bit phits and shifted across the pads under the link's own clock, so a single off-chip memory access takes dozens of core cycles — and the same port, driven from outside, is how a host can write a program image into the chip's memory before releasing it to run. Text output leaves over a UART (universal asynchronous receiver-transmitter), the simplest serial protocol there is: one wire, held high when idle, on which each byte is sent as a start bit (a 1→0 drop that announces "byte coming"), eight data bits, and a stop bit, each lasting one bit cell whose duration is set by the agreed baud rate. There is no shared clock — the receiver times the bit cells with its own clock, which is why clock accuracy (P6) will do real work in this chapter. A JTAG port reaches the standard RISC-V debug module — a five-wire agent that can halt the core, read its registers, and write memory, which makes it both a load path for F and a spec-visible actor. Finally, a custom_boot pin selects the boot behaviour, and a clock tap pin exports an observable copy of the internal clock. Pad functions in this design are fixed — there is no pin-multiplexing machinery — which removes a whole class of configuration-indexed observation problems before they start.

Two properties of trace sets do heavy lifting here and deserve their plain-language forms up front. Refinement (⊑) is the statement "every behaviour of the implementation is an allowed behaviour of the spec" — nothing more; where the spec offers several options (nondeterminism), the implementation may take any. Prefix closure is the property that if a trace is allowed, so is every initial segment of it — in other words, the spec never forbids stopping. That sounds like a technicality until you remember that this machine's power can vanish at any instant: a spec that promised "the UART will print hello" unconditionally would be falsified by pulling the plug mid-hell. Prefix-closed specs make power loss survivable by construction, and the price — the spec can never promise that anything will happen, only that whatever happens is right — is repaid by attaching an explicit time bound T to every liveness claim ("if powered through cycle N, the byte has appeared").

One more translation. The pad voltage is an analog quantity; calling it "0" or "1" is a claim, not a measurement. L0 defines the regimes — voltage-and-stability conditions under which a node counts as logic 0, logic 1, or neither — and obs classifies pad samples through those regimes. Where no regime applies (mid-transition, during power ramps), the trace records that honestly rather than rounding to a bit.

Statement

Define the two objects the overview's top-level statement quantifies over — the map from architecture to pad-level observable behaviour that, before this layer existed, the overview used while nobody defined it.

Sys(F)  =  traces at the pads of:
             ISA (L4)                          the core's contract
           ⊕ SoC memory map                    what each address means      [03]
           ⊕ serial TileLink bridge model      off-chip traffic, phits     [02, 03]
           ⊕ UART model                        the observable output channel [03]
           ⊕ boot machinery (ROM, boot-address the load paths for F, and
             register, custom_boot, debug)     the first fetch             [03]

obs(d,F,E)  =  the physical trace: sampled pad voltages of die d,
               classified through L0's regimes, at L1's clock granularity

Both are definitions; the theorem connecting them is the whole rest of the repository.

The trace alphabet — the load-bearing choice

obs is defined at the physical alphabet: timed, regime-classified pad samples. This is forced, not stylistic, by the epoch analysis (04): an epoch ends in valid-prefix · ramp-down-tail, and prefix closure — the property that lets a machine stop without violating anything — holds at the physical level only. A truncated byte is a prefix of a timed trace but not of any byte sequence, so abstract views (bytes, phits, transactions) are derived, never primitive, or epoch composition is unstatable. (The tail is demonic — adversarially unconstrained, the spec holding under every resolution — only without supervisor + fail-safe-pad discipline; with them it refines to a specified truncate-idle-decay shape — 04.)

Consequences worth pinning:

• The UART channel is a timed trace against the baud clock — bit cells, start/stop framing — with P6's clock-accuracy bound doing quantitative work in the derivation of the byte view. Where framing errors land (open problem: garbage byte vs. excluded-by-derivation) is a real spec decision.
• The serial TileLink channel is a timed trace against the link clock — its phit view and transaction view are two more floors of the same derivation stack, with the clock-domain crossing between link clock and core clock as the validity condition.
• Start of trace: from power-on reset; the boot window before reset release is spec'd by the pads' reset-state defaults and the boot machinery (04's boot-window promise), not demonic.

Refinement shape

obs(d,F,E) ⊑ Sys(F) is trace refinement up to stuttering at the physical alphabet, prefix-closed, with liveness expressed as bounded progress (every claim carries its T). The ε-conditioning lives at the overview's †-lines, not here — Sys itself is a deterministic-spec-with-nondeterminism object, never probabilistic.

Obligations

1. The alphabet definition: sampling, regime classification, the per-pad fixed interpretations.
2. The derivation stack: physical → bit-cell → byte → "the UART printed hello" (and physical → phit → TileLink transaction), each level with its validity conditions.
3. The Sys composition operator itself — how ISA steps, memory-map reads, and device models join into one trace set (the fibred/synchronised product; small but must be written once).

Effort

Weeks; every other L5 file plugs into these two definitions.

L5/01 — The boundary decision

Background

"Verify the processor" is ambiguous in a way that matters enormously, because the thing you might mean by "the processor" comes in at least three sizes, and each size is a different theorem about a different object.

The smallest object is the core: the RocketTile, the generated module containing the pipeline, its caches, and its page of CSRs. A core is not a chip — it is a module with named ports (a clock input, a reset input, a TileLink memory interface, interrupt lines), the hardware analogue of a function that has parameters but has not been called. It cannot run anything on its own; it must be instantiated inside a larger design that connects its ports to actual memory and actual pins. The middle object is the SoC (system-on-chip): ChipTop, which wraps the tile together with the bus fabric, the boot ROM, the CLINT and PLIC, the UART, the debug module, the serial TileLink bridge, and the pad ring — the ring of large driver circuits around the die's edge that turn feeble internal signals into ones strong enough to drive the outside world, and protect the die from it. The SoC is the thing the flow hardens into a layout. The largest object is the device: the packaged chip soldered to a board, next to whatever agent answers the serial TileLink port, a voltage regulator, and a reset supervisor. Only the device is a thing you can hold, and only claims about the device are claims about a computer rather than about a description of one.

Each step outward drags more of the world into the theorem. A claim about the core can assume its memory port behaves (someone else's problem). A claim about the SoC must prove that the surrounding fabric actually delivers that behaviour — but may still assume the far end of the serial link works. A claim about the device must model that far end, the power supply, and the reset circuitry too — and for those parts, which are other people's silicon, no proof is possible even in principle: the best available model is the manufacturer's datasheet, the document stating what the part promises under what conditions. Datasheet-backed models are assumptions, and they are tracked in the axiom ledger under X4. The discipline this chapter establishes is that "the devices meet their datasheets" is never assumed as one blanket axiom, but in per-claim batches: each theorem names exactly which datasheets it stands on.

Statement

The defining scoping choice of the layer: which system the claim is about. Three candidate statements, strictly increasing in strength and in what they drag in:

B3 is the honest end statement and the reason this project is about a computer rather than a core. The plan is B1 → B2 → B3 as successive theorems, each conditional on exactly its batch of X4 models — not one monolithic claim.

X4 as a dial, not a monolith

Each B-level's theorem is conditional on precisely its batch: B1 none; B2 the on-die models (the three SRAM macro kinds — whose own verification is parametric, one proof per kind — and the boot ROM's contents as data); B3 the off-die world (the serial TileLink agent's contract, pad-ring IO cells, the power-on-reset arrangement, the board supervisor). This batching is what keeps X4 honest in Axioms: "the devices meet their datasheets" is never assumed wholesale, only per claim.

What each step buys and costs

B1 is where L3 lands naturally — it is the refinement theorem re-stated at the tile's ports, and needs nothing from this layer except the contract. B2 is the first statement about the hardened netlist: it discharges the bus contract's assume-half against the actual fabric (the contract stops being an assumption), opens the SRAM holes, and pulls in the memory map with its small control devices — boot-address register, tile-reset setter, clock gater, error device. B3 adds the world: pads, the serial link's far end, power epochs, the supervisor — and is the only level at which obs (physical pad traces) rather than an internal interface is the observation.

The mid-level irony worth recording: B2 is about the artifact that gets verified, B3 about the artifact that comes back from the fab. The gap between them is exactly X4's off-die batch plus the pad ring — the part of the world no proof reaches, only datasheets and bench tests.

Obligations

1. Fix the B-level for each publishable claim; never let a theorem's statement straddle levels implicitly.
2. The B1→B2 discharge plan for the bus contract (02).
3. The B3 instance experiment: one hello-world F, the claim stated fully formally (00's derivation stack exercised end to end), even unproven — it will surface every missing definition in the layer.

Effort

The decision: immediate. The B3 instance statement: days, and the highest-value definitional smoke test available.

L5/02 — The bus contract

Background

A bus is the shared pathway over which a CPU reaches everything that is not itself: memories, peripherals, the outside world. "Reaching" something over a bus is a small protocol, not a single act. In this design the protocol is TileLink, the interconnect standard of the Rocket ecosystem: an agent issues a request on its A channel — opcode, address, size, a source ID tag — while a valid/ready handshake governs when the beat transfers; the fabric routes the request to the addressed device, and the response comes back on the D channel, tagged with the same source ID. Cycles spent waiting are called wait states. This channel pair is the entire vocabulary of the interface: everything the core ever learns about the outside world arrives as a D-channel beat with data attached.

The number of wait states varies wildly, and that variance is the crux of this chapter. The tightly-integrated data memory answers in a cycle or two. An instruction-cache refill from the boot ROM crosses the fabric — a handful of cycles. But an access to an address mapped behind the serial TileLink port leaves the chip: the transaction is serialised into 32-bit phits, clocked across the pads at the link's own (slower) clock, served by whatever agent sits on the far end, and returned the same way — easily dozens or hundreds of core cycles, with the exact count depending on the link clock ratio and the far agent. Academic verification work almost universally assumes memory answers instantly; that assumption is false of every real system, and a proof built on it says nothing about the fabricated chip.

The technique for handling an interface like this without verifying both sides at once is assume-guarantee reasoning, and it is used at every interface in this book, so it is worth stating carefully here at its first major appearance. Split the interface's obligations by direction: what the fabric promises the core (the assume half — requests get answered, answers are stable, fetches return the program's actual bytes), and what the core promises the fabric (the guarantee half — requests are well-formed, legal TileLink, source IDs managed, never exceeding the negotiated concurrency). The core's correctness proof (L3) assumes the first half and proves the second; the SoC-level proof (B2 in 01) then proves the first half about the actual fabric, at which point the assumption is discharged and the two proofs compose into an unconditional statement. Each side's proof is finite and local; neither ever has to look inside the other. The one danger in this style — a circularity where each side's promise is justified only by the other's — is avoided here because the split is by polarity: no clause is simultaneously assumed and guaranteed by the same party.

One promise in the assume half is quietly the most important: not that requests are answered, but that they are answered within a bound B. Without a bound, "the processor executes the program" degenerates into "the processor executes the program if the memory ever answers" — a statement with no liveness content at all. Producing that single number (really, a function of the configuration and, for off-chip addresses, the far agent's contract) requires knowing the worst case of everything between the core and the addressed device, and is where this chapter earns its place in the tower.

Statement

Author the contract at the tile's memory port — the formerly orphaned artifact L3 consumes. It is the interface half of Sys: what the fabric promises the core. Authored here, assumed by L3's refinement, discharged against the SoC RTL as part of B2.

Scope note. The tile's ports speak TileLink (L3/06 has the guarantee halves); the clauses below are written in a generic request/response idiom and must be instantiated over the TileLink channel signals — the contract's shape (assume/guarantee split, the latency bound B, the off-chip worst case) is protocol-independent.

The contract

Over the A/D channel pair at the tile boundary:

Assume half (the fabric's promises, this file's content):

A1  every request is answered:  an accepted A-beat gets its D-beat within B cycles
A2  D-channel data is valid and stable when the beat fires
A3  no spurious responses (every D-beat answers an outstanding A-beat,
    matching source ID; no duplication, no invention)
A4  fetches from the boot region return F's contents; accesses to
    serial-TileLink-mapped addresses behave per the far agent's contract
A5  reads/writes to memory-mapped devices behave per the memory map [03]

Guarantee half — the core's request discipline (legal TileLink: aligned addresses, permitted opcodes and sizes, source-ID management within the negotiated bounds) — is morally part of the core's external spec and is proved in L3/06; the contract is the assume-guarantee pair, split by polarity across the two layers.

The latency bound B is load-bearing

Without A1's bound, L3's measure does not exist and "instructions commit" silently weakens to "commit if the bus answers" — the refinement's liveness content hangs on this one number. B's worst case is the off-chip path: an access mapped behind the serial TileLink port becomes a phit-serialised transaction — dozens to hundreds of core cycles, set by the link clock ratio and the far agent's response time. So B is not a constant but a function of the configuration — clock gating state, link clocking, and for off-chip addresses the X4 contract of the far end — one more register-dependent hypothesis, resolved the same way as the other configuration knobs (05): either quantify over reachable configurations or declare the excess out of spec.

Most academic work assumes a magic single-cycle memory — a load-bearing cheat this file exists to avoid. The contract's entire point is that the fabric's real behaviour (wait states, arbitration among the tile, the debug module, and the inbound serial-link master; the DTIM's near-single-cycle path vs. the serial link's dozens) fits behind five clauses and one bound.

Discharge at B2

Against the SoC RTL: the fabric between tile, memories, and peripherals is ordinary synchronous logic, so A1–A5 become invariant-style lemmas about it — with A4's off-chip side remaining conditional on the far agent's model (X4's B3 batch) while the bridge's serialisation behaviour is B2-provable RTL. The split point (bridge proved, far agent assumed) should be marked in the clause itself.

Obligations

1. The five clauses stated over the channel alphabet, with B(config) explicit.
2. Check against the tile's TileLink transactions in simulation (days — the L5-unblocking experiment).
3. The B2 discharge lemmas; the A4 split point marked.
4. Arbitration: whether an inbound serial-TileLink master or the debug module can starve the tile (an A1 threat — if the fabric's arbitration admits starvation, B is conditional on those agents' quiescence, which must then be a recorded spec condition).

Effort

Days to author; the discharge is B2 work. The arbitration check (4) is the one place a surprise could hide.

L5/03 — The memory map

Node: this file is the object — the memory map, IRQ/pad tables, and the RTL-vs-metadata diff that pins them. The device models that compose with the ISA into Sys are the edge, 06.

Background

A CPU core has no instructions for "print a character" or "read a pin." It has loads and stores, and nothing else — so systems are built on a convention called memory-mapped I/O: regions of the address space are wired not to memory but to devices, and a store to such an address flips wires in a peripheral rather than writing a byte to RAM. A store to the UART's data register starts a byte transmitting; a load from the CLINT's mtime registers reads the running timer; a store to the tile-reset setter holds the processor in reset. The memory map is the table saying which address ranges mean what — and since the CPU's view of the entire world is filtered through it, a verification effort that gets the memory map wrong is proving theorems about a different machine.

The devices behind those addresses each need a formal model — a small transition system saying how register writes translate into behaviour. For the UART that means the divisor register (the programmable number that sets the baud rate by dividing the bus clock) and the framing sequence: on a write to the transmit register, the TX wire emits start bit, eight data bits, stop bit, each lasting divisor clock cycles. Interrupts are the other direction of device communication: rather than the CPU polling devices in a loop, a device raises a dedicated wire when it wants attention, and the CPU suspends the program to run a handler. In this design the wiring is the RISC-V standard shape: the CLINT drives the core's software and timer interrupt lines, and the PLIC funnels device interrupts (here just the UART) into the external-interrupt line, with a claim/complete protocol replacing ad-hoc pending registers.

There is also a fact about where this information lives that deserves a newcomer's attention: the map is generated. The SoC is elaborated from parameterised Chisel generators, and the address assignments come out of the elaboration (the framework's diplomacy layer negotiates them); the same run emits the decode logic in the RTL, a device tree describing every device and its range, and per-device register-map JSON files. Agreement among these artifacts is claimed by construction — they are renderings of one elaboration — and that is precisely the kind of claim this book checks rather than assumes: the diff of the RTL's actual decode against the emitted metadata is this chapter's first deliverable, and any drift is an elaboration bug worth a finding.

Statement

The remaining components of Sys: what each address means, what each device does, and which pad carries what — consolidated from the generated sources into one formal object, diffed against the RTL rather than trusted.

Where the information lives today

The concrete map, from the generated device tree of this configuration:

The hole semantics matter to 02's contract and are better-behaved than most systems: the fabric routes accesses to unmapped space to the error device, which answers with a TileLink denied response, and a denied response to a load raises an access fault in the core — so a stray pointer produces a precise architectural exception, not a hang or a silent 0xFFFF_FFFF. The address-decode model must say so, and the error device is thereby a spec component, not scenery.

The device models that turn these addresses into behaviour — UART, IRQ/CLINT/PLIC, boot, serial TileLink — and their composition with the ISA into Sys are the edge that this map carries, 06.

Obligations

1. The RTL-vs-metadata diff for map, IRQ wiring, and the port list — re-anchoring the layer's checker to the generated artifacts; agreement is expected, and drift is a finding about the generator.
2. Track the elaboration-emitted map against the hardened netlist's decode — the elaboration is authoritative for intent, the netlist for the artifact; synthesis must not have changed the table.

Effort

Weeks, mechanical; the map is the extracted table plus the two diffs that pin it. The device models that compose it into Sys are the edge, 06.

L5/04 — Power epochs

Background

Nothing in an ISA manual says what happens when you turn the computer off, because from the software's point of view nothing can happen — there is no software anymore. But a theorem about a physical chip has no such luxury: power arrives, wanders, sags, and vanishes on the environment's schedule, and the spec must be true through all of it. This chapter is about the machinery — physical and logical — that makes that possible, and it uses a vocabulary of small analog circuits that deserve introduction.

Start with what actually happens at power-on. The supply voltage does not appear; it ramps, over milliseconds, through every value between 0 and 1.8 V. During the ramp the chip's logic is in no valid state — flip-flops wake up holding arbitrary values, and below operating voltage the gates cannot even be trusted to compute. The standard remedy is a power-on reset (POR) circuit: a small analog block that holds the chip's reset line asserted from the moment any power exists until the supply has been stable for a while, then releases it once, cleanly. On release, every register with a reset connection loads its defined initial value, the program counter points at the boot address, and execution begins. One continuous run — from that release until power goes away — is what this book calls an epoch; the chip's lifetime is a concatenation of epochs separated by dark gaps, and the top-level theorem, which covers one epoch, must be composed across them.

The genuinely nasty case is not power loss but power sag — a brown-out. Flip-flops retain their state down to a voltage well below the minimum at which logic operates correctly. Between those two thresholds lies a gray band: a supply excursion that dips into it and recovers leaves the machine with silently corrupted state, still running, having triggered nothing — neither a clean death nor a valid continuation. The standard industrial defence is a brown-out reset (BOR) or supervisor: a cheap, self-contained part (on-board or on-die) that watches the supply rail with an analog comparator and asserts reset the moment the rail leaves the valid range, holding it until the rail has recovered and settled. Whether such a part actually closes the gray band — including the awkward regress that the watcher is powered by the rail it watches — is the substantive question this chapter answers.

Two more pieces of bench vocabulary. The decoupling capacitors ("decaps") scattered across the die in their tens of thousands are small charge reservoirs that smooth the supply against fast demand spikes; here they acquire a third formal job, as the energy store that guarantees the supervisor wins its race against a collapsing rail. And a hold-up capacitor is the same idea writ large at board level: a bulk capacitor storing enough energy that, when the input power fails, the chip has a known number of milliseconds of clean supply left — enough, if a warning signal fires, to finish the byte in flight and park somewhere quiet instead of dying mid-symbol.

Statement

The top-level statement covers one powered epoch: POR-released reset through T in-envelope cycles. The lifetime claim is a concatenation — obs = boot·trace₁ · gap · boot·trace₂ · … — and this file owns its composition: the per-boundary requirements, how power meets the ISA, and the brown-out resolution.

Per epoch boundary

• V8 (L0/04): supply ramps follow the sequencing/rate constraints — the transitions between U and powered are trajectory conditions the steady-state envelope does not cover (multi-rail bring-up can forward-bias junctions and reach latch-up's branch while the wells are not yet protected).
• The POR contract (X4-class): this design carries no analog POR block of its own — the arrangement lives in the pad-frame harness or on the board — so the contract is assumed, in its standard shape: reset asserted from power-good to supply-stable, released synchronously with a running clock, once.
• Per-epoch X-elimination, refined by the spec: reset drives definite only what Sys(F) claims definite (pc, FSM, reset-defined state); elsewhere implementation-X is matched by the ISA's reset nondeterminism (L3/03's three-way split). The proof quantifies from all-X ⊇ arbitrary garbage, so brown-out recovery and SEU-recovery reset share this one obligation.
• The boot-window promise: the pads have fixed functions and reset-defined drive states, so obs during boot is spec'd by hardware defaults, not demonic — the obligation is to extract and check those defaults from the RTL (UART TX idle-high, the serial link's valid lines deasserted, JTAG TDO passive).
• How F persists. This chip has no writable persistent store: the boot ROM's contents are fixed at mask time (immutable by construction — the strongest possible answer to the F-evolution question), the data memory is volatile, and anything beyond the pads is X4's business. So the epoch-composition theorem carries one of two hypotheses: F is ROM-resident (immutability free), or F is loaded each epoch over the debug module or serial link — in which case "the same F arrives every epoch" is an explicit assumption on the environment, exactly the kind of clause that belongs in the composition rather than in anyone's intuition. Crash consistency, the deep problem writable persistence forces, simply does not arise on-die.
• ε sums over powered time; aging (electromigration, NBTI, thermal cycling) scopes P4/P5 to the die's rated lifetime — the honest horizon of the whole theorem.

One power domain. The design has a single core rail — no mid-epoch domain switching, no power islands — which deletes the partial-cycling containment obligations that multi-domain chips carry. (The gap between core rail and IO rail still exists, and returns below as the partial-rail fault.)

How this meets the ISA — which is rightly silent

The ISA's two hooks suffice: its reset section is the power-on hook, and prefix-closed small-step refinement is the power-off hook — a machine that stops violates nothing. Three consequences with teeth:

1. The epoch's end is prefix · demonic-ramp-down-tail · U (a dying UART TX can glitch a start bit), so prefix closure must hold at the physical alphabet with byte views derived — the constraint that forced 00's alphabet choice.
2. All liveness is bounded progress ("if powered through cycle N, O by N") — power persistence becomes a per-claim P6 assumption, delivered free by the explicit T every statement already carries.
3. Crash consistency is out of scope on-die (no writable persistence); whatever sits across the serial link owns its own persistency model (X4).

The brown-out gray band, and its resolution

Sudden full loss is the easy case. The epoch model is unsound against a slow sag below operating minimum but above state retention, recovering without reset — corrupted state, continued execution, neither epoch end nor valid continuation. An RC-ramp POR does not cover the band. The discharge is a supervisor (on-board, X4-class, jellybean part): (A) reset-clamp BOR — assert throughout the excursion, release on hysteresis + timeout — or (B) forced full discharge — load switch + bleed drains the die below retention on any sag, deleting the gray band from the reachable states rather than guarding it.

Rail faults do not go into ε — by category. ε's terms share one shape: continuation despite corruption (SEU, unresolved reads, evading droop) — the machine keeps running with traces that look valid but aren't. A rail fault is terminal, and termination is already free: prefix closure + the specified backstop tail make a fault death ⊑ Sys(F) with probability 1; adding a λ_fault·T term would pay probability for behaviour the spec can admit. (The claim is conditional correctness — while it runs, and however it stops, the trace is in-spec — not availability; component MTBF is a different document.) Three corner checks: the fast-collapse garbage burst (a short crossing the gray band faster than t_detect) is energy-bounded, hence deterministic — the tail admits "≤ t_burst of sub-symbol activity," filtered by the byte-view derivation, rate-independent; recovering transients that evade the BOR are exactly P_droop, which the supervisor shrinks rather than adds to; and the one real gap is the partial-rail fault (core dead, IO alive — level shifters float, output stages still driving): neither terminal nor bounded, engineered away by the fail-safe-IO property in its literal datasheet sense (pads hold safe state with the core unpowered) — an X4-class per-cell property of the sky130_fd_io macros — else it alone would genuinely need a component-FIT ε term.

The apparent regress (the detector is powered by the failing supply) terminates by range stacking + fail-safe polarity: the analog detector's validity range strictly contains the logic's gray band, and below the detector's own floor, deasserting reset requires drive headroom that no longer exists — a passive pull holds reset asserted. The requirement is "output monotone-safe in Vdd," one-sided, an easier computer-assisted-proof target than the oscillator (DC maps + latency bound; M8's interval machinery). Two checkable inequalities close it: traversal — t_detect + t_reset_prop < C·(V_thresh − V_fail)/I_max with C the decap total (the decaps' third formal job) — and hold — reset held past state-death or POR stabilisation. Residue: async-reset assertion effective at degraded voltage (one-sided DC-drive argument, not a timing race).

Hold-up energy makes the common death graceful. One rung above the tamed tail: a bulk capacitor plus an upstream power-fail warning (watching the input, before the storage — the BOR stays on the die rail as backstop) buys a bounded epilogue on stored energy: finish the symbol in flight, refuse new work, park at a quiescent state, then decay. The governing inequality t_holdup(C, I, ΔV) ≥ t_epilogue^max has its right-hand side derived from L3's exported WCET table (L3/08's quantitative reading of the measure): worst-case cycles over the epilogue path with IRQs masked, times a clock-period upper bound valid over the decaying-rail trajectory — the clock source slows as the supply sags, so the seconds-per-cycle factor is taken at the worst voltage the epilogue traverses (V8's temporal sibling). The refinement's own progress bound thus prices the capacitor (µF-scale at this design's draw; a UART byte at 9600 baud ≈ 1 ms ≈ tens of µF), and "we can finish the job in time" is a theorem, not a characterisation. Epilogue routes: warn→IRQ→firmware (drags firmware into the claim) or a hardware quiesce — gate issue at the next commit and drain — bounded by construction; a minor design modification of the kind the project's framing permits. The epoch end then refines once more, warn · epilogue · quiescent-end · decay: a spec event, not a truncation — B3 strengthens to "the last accepted byte is always fully emitted." Structurally this is the boundary ladder's move in the power domain: stored energy converts an asynchronous environmental event into a bounded-latency protocol event, price paid in board space instead of ε. Honest limit: gracefulness is conditional on the failure mode — upstream loss (the common case) goes graceful; a rail fault discharges the hold-up instantly, so the spec keeps a two-tier ending with the truncate-idle-decay tail as the rail-fault backstop.

Good BOR also tames the demonic ramp-down tail. The tail's demonic-ness came from one scenario — the core executing garbage in the gray band while driving pads — and the BOR threshold sitting above that band deletes it: normal operation ends at BOR assertion (in the valid band, pads driven to reset defaults correctly), and below the valid band the chip is already in reset with fail-safe polarity holding. The tail refines to (≤1 truncated symbol) · idle^k · monotone decay — specified, not demonic — under two pad-side conditions: (i) reset defaults are non-hazardous — to be checked in the RTL, with the expected answer that no output pad actively drives a hazardous level at reset (UART TX idles high, so the worst case is one framing error, never a spurious start bit); (ii) the IO cells are fail-safe under collapse — a constant-input driver must not glitch as rails die, with the core-before-IO level-shifter float as the known hazard — an X4-class per-cell property, plus V8 extended to the down-ramp rail ordering. Under architecture (B) even the decay profile is board-controlled (the bleed sets dV/dt). Irreducible residue: truncation timing (environmental), the analog decay (specifiable, not digital), and the fail-safe-IO property itself. The B3 payoff: "under power loss at any point, at most one framing error and never a spurious character" becomes provable rather than caveated.

Obligations

1. The epoch-composition theorem over 00's alphabet: per-epoch refinement + the boundary requirements ⟹ the lifetime claim.
2. The F-persistence hypothesis: state the ROM-resident and reloaded-per-epoch variants, and for the latter the environment clause that carries it.
3. The supervisor's two inequalities, computed from datasheet + decap numbers; the monotone-safe property as a CAP target.
4. The pad reset-default check against the RTL (the boot-window promise's evidence).

Effort

The composition theorem: weeks once 00 exists. The checks: days each. The supervisor CAP proof: optional depth, L0-machinery.

L5/05 — The operating-conditions clause

Background

Every datasheet has a table called recommended operating conditions: supply voltage between here and here, temperature between here and here, clock no faster than this — and every other promise in the document is implicitly conditional on that table. This chapter builds the formal analogue of that table, and the reason it is needed is a fact about modern chips that surprises outsiders: software can reconfigure the hardware out from under its own correctness proof.

The mechanism is configuration registers: memory-mapped registers whose bits are wired to physical knobs. The sharpest instance on most chips is the clock — a software-programmable PLL whose settings can shrink the clock period below what the timing proof covered. This design does not have one: the core clock arrives at a pad from the board, unmultiplied, so the most dangerous knob of all is simply absent, and "the clock is in range" moves out of the register table entirely — it becomes a condition on the environment (the board's promise, P6's family), not on reachable software states. What remains software-reachable is tamer but real: a clock gater that can stop the clock, a tile-reset setter that can hold the processor in reset, the UART's divisor register on which the byte view's validity depends, and the debug module, an external agent with the authority to halt the core at any time.

So hypotheses of lower-layer theorems turn out to depend on register state, which makes them reachability conditions: either prove the hypothesis for every register value the software can actually reach, or draw a line — inside the line, the spec's promises; outside it, explicitly no promises. The second option is what this chapter constructs, and it must also say precisely what "no promises" means. The answer deliberately falls short of the C programmer's "undefined behaviour" (where the spec permits literally anything): here, out-of-condition operation floods the machine's state with unknowns, but the electrical safety envelope still holds — a misconfiguration computes garbage or stalls, it does not damage the die — and a reset restores the machine to the specified regime. Garbage, bounded, recoverable: weak enough to be true, and deliberately too weak for anything safety-critical to lean on.

Statement

Sys(F) must take a stance on every software-reachable knob that can invalidate a lower layer's hypotheses — the theorem-shaped version of a datasheet's "recommended operating conditions" table. An S4-class authored choice; deciding it early keeps the overview's metatheorem free of design-specific side conditions on F.

The pattern, and its known instances

Register-dependent hypotheses of lower-layer theorems become reachability conditions. Per knob, exactly two discharge routes: prove the hypothesis over every reachable setting, or declare the excess unspecified in the spec.

Notably absent from the table, by design rather than by luck: a clock multiplier (none exists — the board owns clock safety), pad function muxing (pad functions are fixed), and persistent-store write paths (there is no writable persistent store — 04). The table is expected to grow one row per discovered knob; the file exists so the later instances are filing operations, not rediscoveries.

What "unspecified" means — precisely, and deliberately weakly

Not C-style undefined behaviour. Per L1/03's value lattice: the state floods with X — envelope-bounded demonic nondeterminism. The damage tier (L0/04's V-conditions) is still excluded — an out-of-spec configuration computes garbage, it does not burn the die — and recovery is provable: restore the configuration, reset, and X-elimination re-enters the tracked fragment. So the clause's semantics is: outside recommended operating conditions, Sys(F) constrains obs only to the electrically safe trace set, until the next reset re-anchors.

This weakness is a feature twice over: it is true of the physics (the envelope genuinely still holds), and it keeps the UB clause from ever being load-bearing for safety-critical reasoning — nothing above may assume out-of-spec behaviour is absent, only that it is recoverable. The same layered-UB pattern appears one level down in L4/03's spec-UB clause for reserved instruction encodings: at every layer, "undefined" means undefined at this layer's alphabet, bounded by all the layers below — no knob and no instruction is a halt-and-catch-fire.

Obligations

1. The clause itself, as a component of Sys: the recommended-conditions predicate over configuration state, and the X-flood semantics outside it.
2. Per-row resolution: the gating/reset liveness conditioning, the divisor's validity condition, the debug-halt actor model.
3. The audit discipline shared with L4/02: no lower-layer proof may consume a register-dependent hypothesis without a row here.

Effort

Days for the clause; the rows resolve at their owning layers. The value is the slot: every future knob lands in a named place.

L5/06 — The device models

Edge: this file is the theorem the node carries — the device models (UART, IRQ/CLINT/PLIC, boot, serial-TileLink) that compose with the ISA into Sys (ISA ⊕ devices ⟹ Sys), the composition edge. The memory-map object they attach to is the node, 03.

The models to write

Memory map: an address-decode function addr → (region, device, offset) — extracted from the RTL's decode logic and diffed three ways against the device tree and the register maps; then cast as the formal decode component, including the error-device routing on holes, exported to 02's A5 and to L3's load/store lemmas. The extracted table itself and its RTL-vs-metadata diff are the node's, 03; here it enters the composition.

The IRQ map: which physical event drives which line of L4/01's interrupt array — the system half of interrupts, deliberately not in the portable spec. The shape is standard RISC-V: CLINT compare drives mtip, CLINT software-interrupt register drives msip, and the PLIC drives meip, with the UART as PLIC source 1. Where an interrupt persists is the PLIC's gateway-and-pending machinery (level-triggered gateways, claim/complete, priority threshold) — L4/01's pending CSR is a live view — so the PLIC model is a required component of Sys, carrying the no-lost-interrupts half of L3/07's delivery obligation.

UART: the observable channel — divisor register semantics, bit-cell generation against the bus clock, transmit/receive FIFOs and watermark interrupts, the TX trace feeding 00's derivation stack; RX's synchroniser is L1/11's business, its byte semantics here.

Boot machinery: the ROM's contents as data, the boot-address register, and the custom_boot pin — together they determine the first fetch address and hence what "with image F" means in every end-to-end statement; the load paths (resident ROM, debug-module writes, serial-link writes) are each a spec-level way for F to arrive.

Serial TileLink bridge: phit serialisation and clock crossing on the chip side — the piece that turns 02's B(config) into a function of the link clock ratio; the far side is X4.

Obligations

1. The five models above as components of Sys's composition (00 obligation 3) — for the map, that is the extracted table plus the error-device semantics on holes, as a formal decode function. The extraction and diff of that table are the node's, 03.

Effort

Months, wide and mechanical; the models are small individually and the composition into Sys is the deliverable. The memory-map object and its diff live in the node, 03.

L4 — The ISA specification

Node — the ISA: ISA = Sail-RV32(config, incl. machine mode) ⊕ authored residue ⊕ S4-choices (00–03) — the transition system L3's invariant refines into, and the core of L5's Sys(F). Edge up: none of its own — L3 carries the refinement up into this node, and L5 carries the ISA ⊕ devices ⟹ Sys composition out of it. A definition node — specification authoring, not proof; the place where being wrong is least detectable, because a wrong definition yields a true theorem about the wrong machine. Consumes: the RISC-V standard, the configuration record.

Background

An ISA — instruction set architecture — is the contract between hardware and software: the instructions, their encodings, and their exact effects on architectural state. This layer fixes that contract as a mathematical object, because L3's refinement theorem is only as meaningful as the spec it refines against. The object has three components with three different levels of trust: RISC-V's official formal model is imported — the base ISA and, because the shipped core implements the standard machine-mode trap machinery, the ratified machine-mode subset of the privileged architecture with it (00); the small pieces of behaviour that live outside the ratified model — the generated core's custom extension and the platform interrupt controllers' register conventions, chiefly — must be authored or imported from de-facto documents (01); and where the standard is deliberately loose, the choices this implementation embodies are recorded rather than silently assumed (02). A totality sweep (03) then makes the spec answer for all 2³² instruction words, not just the meaningful ones.

Statement

What L3's theorem is stated against: Sail-RV32(config) ⊕ authored residue ⊕ S4-choices ⊕ spec-UB clause — the last assigning the reserved encoding space unspecified behaviour (03) — its authored components carrying the three fidelity axioms — S2 (the official model's small residue, now covering the machine-mode subset as well as the base), S3 (the authored residue: the custom extension and anything else outside the ratified model), S4 (the recorded choices). It is not the top of the tower — the pad-level system spec is L5's — and the boundary test is portability: the same core in a different SoC keeps this layer's spec while L5's is replaced wholesale.

Subcomponents

Interfaces

Consumes: the standard, sail-riscv, the configuration record (which derives the subset boundary), the RTL + generator sources + test software as S3's anchors. Exports: ISA to L3 (refinement target) and L5 (core of Sys); the partition of the encoding space to L3/10; the choice register to L3's lemmas.

Axioms introduced

S2 (Sail faithful — small: the model is the standard's official golden model; residue is fidelity to the ratified manuals plus the pinned translation path — now covering the machine-mode subset too), S3 (the authored residue is what was intended — unfalsifiable, anchored), S4 (the recorded choices are acceptable — legislative by nature). X4 lives in L5.

The layer's shape

Entropy sorted by kind: 00 receives the bulk for free (official golden model, structured encoding space — and, for this core, the trap machinery too), 03 turns the remaining width into independent SAT-shaped typing, and the thinking is deliberately concentrated into two small artifacts — 01's authored residue and 02's choices — because those are the two places an error is invisible downstream. The honest end statement this layer serves: not "the core is correct" but the device refines this specification, modulo these axioms — with unbounded proof capacity the axiom list is the achievement, which is why axioms.md precedes any proof.

The ISA is rightly silent about power: its reset section is the power-on hook (X ⊑ reset nondeterminism), prefix-closed small-step refinement is the power-off hook; everything else power-shaped is L5's epoch model. Resist adding power events here — the layering is doing its job.

Open problems

1. Author the residue (01) — gates L3/07; the highest-risk specification work left in the layer.
2. Seed and enforce the S4 register (02) before L3's proofs start.
3. The Sail→prover translation's trust status, pinned and stated (00) — now including the privileged-subset clauses.

First experiments

• Import sail-riscv at a pinned commit, carve the configuration's subset, and run the architectural compliance suite against the imported model (00) — the only handle on S2.
• Draft the custom-extension residue from the generator source first, then diff against the emitted RTL's behaviour; log every discrepancy (01).
• Generate the encoding partition from the configuration record (03).

Effort

6–9 months. Small in proof content, disproportionate in consequence: an error here is invisible to every layer below and produces a true theorem about the wrong machine.

Reading

sail-riscv and the Sail language papers. The RISC-V unprivileged spec (Volume I) and the machine-mode chapters of the privileged spec (Volume II) — both short and readable, and 00's tour is a map into them. ARM's CHERI/Morello work — the best existing example of an ISA-level property proved against a shipping architecture spec.

L4/00 — RISC-V's structure, and its Sail formalisation

Background

An ISA — instruction set architecture — is the contract between hardware and software: the complete list of instructions a processor executes, what state they act on (registers, the program counter, memory), and exactly what each one does to that state. It is the one interface in computing with different vendors on each side — compilers target it, processors implement it, and neither party ever sees the other's internals. RISC-V, the ISA of this project, is distinctive in being an open standard: its specification documents are public, governed by a nonprofit, and implementable by anyone without a license — which is why open-source cores like Rocket can exist at all.

For most of computing history, ISAs were specified in English. An instruction's behaviour would be given as a page of prose plus a register-transfer sketch, and the thousands of edge-case questions (what does a shift by 32 do? what happens to the upper bits? in what order do a trap and a pending interrupt resolve?) were settled by tribal knowledge, reference implementations, and vendor errata. A refinement proof cannot consume prose. It needs the ISA as a mathematical object — a transition system: a set of states and a step relation, in which "execute one instruction" is a defined function of the current state. Producing that object by hand from the manual would itself be a large, error-prone authoring job, and any mistakes would be specification errors — the kind no downstream proof can catch, since the proof would faithfully verify the processor against the wrong contract.

This is what Sail exists to fix. Sail is a programming language purpose-built for writing ISA specifications: a spec written in it is precise (every bitfield, every corner case forced to a decision), executable (you can run programs against the spec and compare with real hardware), and mechanically translatable into the input languages of proof assistants. The RISC-V organisation took the further step that matters most here: it adopted a Sail model, sail-riscv, as the standard's official formal specification — the "golden model" against which conformance is judged, with new extensions required to extend it for ratification. (The ratified prose manuals remain the normative documents; the model is the standard's own executable reading of them.) This chapter's job is to import that model, pin down what "import" means (which translation, which version, what is trusted about it), and carve out exactly the fragment this small core implements.

One structural fact to hold on to before the details: a RISC-V instruction is a 32-bit word, and the specification of the ISA has two separable halves — the encoding (which bit patterns denote which instructions, with operand fields at fixed positions) and the semantics (what each instruction does). Keeping the halves separate is what makes it possible to say, later, that the compressed extension adds new encodings but no new semantics, and that the decoder and the executor generate independent proof obligations.

Statement

Import Sail-RV32(config) — the base ISA and the machine-mode subset of the privileged architecture — as the received core of ISA. First, fix what the object being imported is, since the standard's structure is what makes the import modular and the subsetting principled.

How RISC-V is structured

Two volumes. The unprivileged spec (Volume I): the instructions a program sees. The privileged spec (Volume II): machine/supervisor modes, CSRs, traps, virtual memory. This core implements Volume I's base and extensions plus Volume II's machine-and-user-mode fragment — the trap/interrupt CSRs, PMP, and their semantics, declared by the elaboration and to be confirmed by the configuration record — and nothing above it: no supervisor mode, no virtual memory. So the import cuts inside Volume II, at the machine-mode boundary, and the subset must be carved by CSR rather than by volume.

Base + extension letters. A base ISA (RV32I: ~40 instructions — integer ops, loads/stores, branches, jumps) plus optional extensions, each a letter with its own ratification: M (multiply/divide), C (compressed 16-bit re-encodings), Zicsr/Zicntr (CSR access / counters), and many more (A, F, D, V…). The letters are the configuration vocabulary, and this core's string — declared by the elaboration itself — is rv32imac_zicsr_zifencei_zihpm_xrocket: the base plus multiply/divide, atomics, and the compressed re-encodings, plus CSR access, fence.i, and the performance counters — with the trailing x marking the custom fragment that 01 owns. Every absent letter (F, D, V, S-mode…) is spec the import does not carry and the coverage sweep must instead prove traps.

The encoding space. 32-bit words with [1:0] = 11 (the other three values are the compressed quadrants); major opcode in [6:2]; then six formats fixing where operands live:

R:  funct7 | rs2 | rs1 | funct3 | rd | opcode      register-register
I:  imm[11:0]    | rs1 | funct3 | rd | opcode      register-immediate, loads
S/B:  imm split around rs2|rs1, funct3, imm|opcode  stores / branches
U/J:  imm[31:12]              | rd | opcode         lui, auipc / jal

The immediates in S/B/J are bit-scrambled — deliberately, so that register fields sit at fixed positions and the sign bit is always bit 31: the standard is shaped for cheap decoders, and the scrambling is spec content the decode lemmas must get right. The space reserves custom-0/custom-1 major opcodes for vendor instructions; the shipped core uses none of them — its custom behaviour lives entirely in CSR address space (the two external-interrupt array registers, 01), which is the tamer kind of custom: no new encodings, no new step relation, just two more registers with authored semantics.

How Sail specifies it — a worked example

sail-riscv organises each instruction as three clauses: an AST constructor, a bidirectional encode/decode mapping, and an execute function clause. For addi (I-format, major opcode OP-IMM, funct3 000), lightly abridged:

union clause ast = ITYPE : (bits(12), regidx, regidx, iop)

mapping clause encdec =
  ITYPE(imm, rs1, rd, RISCV_ADDI) <-> imm @ rs1 @ 0b000 @ rd @ 0b0010011

function clause execute (ITYPE(imm, rs1, rd, RISCV_ADDI)) = {
  let result : xlenbits = X(rs1) + sign_extend(imm);
  X(rd) = result;
  RETIRE_SUCCESS
}

Three properties of this shape matter to the project. The encdec mapping is bidirectional, so decode totality/injectivity are properties of the clause set — exactly what L3/10's decode bijection is checked against. execute is a state transformer over X (the register file, with X(0) hard-wired zero) and PC — the transition system L3's α lands in. And RETIRE_SUCCESS vs. trap outcomes is the retirement event RVFI observes — the three-way agreement (Sail retirement, RVFI, α's commit points) is one object seen three ways.

A branch (beq, B-format) adds the two remaining ingredients: the scrambled immediate reassembled in encdec, and a conditional PC update in execute — together with addi it exercises every structural feature the other ~40 instructions repeat.

Why the base is real, and the import path

sail-riscv is the standard's official golden model — adopted by RISC-V International, with extensions required to extend it for ratification — which makes S2 smaller than it looks: its residue is the model's fidelity to the ratified manuals plus the translation path. Mitigation: run the official architectural compliance suite against the imported model (post-translation, in our prover), not against upstream. The Sail→prover translation (which backend, which version, deep vs. shallow, how Sail bitvector primitives map) is conventionally trusted; state it as S2's ledger line and pin it like the toolchain.

Subset by configuration, not by hand: the implemented/unimplemented boundary is derived from the configuration record and exported to 03 — a hand-maintained list would drift. The machine-mode carve is part of the same derivation: exactly the measured CSR set, with reads of absent CSRs (mscratch, misa, the counters) landing in the trap sweep.

Deliberately out of scope

The memory model (RVWMO — axiomatic↔operational equivalence plus a multicore RTL refinement, unattempted at any scale), virtual memory, floating point, supervisor mode, and PMP. The shipped core has none of them, and the import cuts at the machine-mode boundary — everything of Volume II above that line stays out.

Obligations

1. The pinned import with the translation's guarantees written down.
2. The compliance-suite harness against the imported model.
3. The configuration-derived subset boundary.
4. The addi/beq worked pair as the first end-to-end spec objects — cheap, and they template the rest; a trap-entry/mret pair from the machine-mode subset alongside them, since the privileged clauses are new to the import.

Interface (up). The imported model is one half of the S-isa seam (iface_L4_L5, archBeh = isaBeh): the reference isaBeh the microarchitecture must equal at the pad boundary, bundled with the L5 memory map and devices. Its fidelity to the ratified standard is the specification-side axiom S2.

Effort

Weeks to import and pin; the compliance harness is the substantive piece.

L4/01 — The authored residue (S3)

Background

Almost everything the core does is covered by the ratified formal model: the base instructions, the M/A/C extensions, the machine-mode CSRs, trap entry and mret are all imported spec (00). But no real chip sits entirely inside a standard, and the parts that poke out must have their specification authored — written here, by this project, with no external document to defer to. Authoring a spec for hardware you can inspect carries a well-known trap: the natural move — read the RTL, write down what it does — produces a spec that agrees with the implementation by construction, and a refinement proof between them verifies nothing at all; bugs get transcribed into the spec and then formally certified. The field calls this "verifying the implementation against itself," and the defence is discipline about evidence: gather every description of intended behaviour that is independent of the RTL — generator sources, documentation, conventions, software written against them — formalise those first, and treat every point where the RTL disagrees as a finding to adjudicate deliberately, never a detail to silently copy.

For this core the residue is smaller than a custom design would carry, and its members are declared rather than hidden: the ISA string the elaboration emits — rv32imac_zicsr_zifencei_zihpm_xrocket — ends with a custom extension marker, and that x is precisely where the authored spec lives. Around it, the residue inventory:

• The xrocket fragment. The generated core carries implementation-control state outside any ratified document — custom CSRs of the "chicken bit" family (feature-disable and implementation-control registers) and any custom instructions the generator emits. The first obligation is an enumeration: diff the RTL's CSR and instruction decode against the ratified set; every hit is residue to author, from the generator source first.
• The performance-counter event space (Zihpm). The counters themselves are ratified; which event each selector value counts is implementation-defined by the standard — an authored table, extracted from the generator's event wiring.
• The debug module (RISC-V Debug specification, v0.13 family) can reach architectural state out of band. Its own register model is imported from the debug spec — a de-facto-standard document rather than the ISA manuals — and it is excluded from ISA proper by the debug-inactive conditionality (L3/06) rather than specified here.
• Interrupt sources are not residue — a genuine simplification worth recording. The software, timer, and external interrupt pending bits are all live and all standard; what drives them (CLINT compare, CLINT software-interrupt register, PLIC claim/complete) is device behaviour behind the memory map, specified as L5/03's models. The core-side interrupt spec is imported intact, and dispatch beyond mcause's external-interrupt code is software's business via the PLIC.
• The reset vector is a constant (the boot ROM's entry), matching the standard's platform-constant expectation — the software-visible "boot address" indirection is an ordinary device register (L5/03), not a parameterisation of the spec's reset section.

The ⊕-extension mechanism must still support override, not just extension: wherever measurement shows the implementation deviating from the imported model's ratified behaviour, the spec must either record the deviation explicitly as an override (making it S3-authored content with its own evidence trail) or treat it as a bug to fix upstream. No such deviations are currently pinned for this core — the ratified trap surface (access faults from denied bus responses included, misaligned loads and stores trapping, ebreak raising cause 3) is the expected answer — but "expected" is exactly what the diff exists to check, and the deviation log starts empty rather than assumed empty.

Statement

Author the residue: the spec fragments for exactly the behaviours outside the ratified model, composed with the Sail import as ⊕-extensions (with override capability). S3 is the axiom that this authored fragment is what was intended — unfalsifiable in the same sense as any specification-fidelity claim, and priced in the register.

State. The custom-CSR file of the xrocket fragment (enumerated, then specified register by register) and the Zihpm event-selector table.

Steps / invariants — the discipline the RTL diff must settle rather than assume:

• Custom CSR accesses obey the standard CSR access rules (privilege, read/write legality) with the authored per-register semantics.
• Implementation-control CSRs may change performance, never architecture: the authored spec must say explicitly that every reachable setting preserves the refinement (or name the settings that do not, which then become operating-conditions rows — L5/05).
• The event-selector table is total over the selector values software can write, with unmapped selectors counting nothing.

Authoring methodology: breaking the circularity

The spec and the implementation cannot share their evidence. The anchors, in order of independence:

1. The generator source: the Chisel CSR file and decode are the design intent — formalise the custom fragment from them first, then diff the formalisation against the emitted SystemVerilog's behaviour (a generator bug would surface as exactly that diff).
2. The ecosystem's software: the standard test suites and the framework's own bring-up code are written against the intended semantics; the spec must make observed, working behaviour correct.
3. RVFI-style retirement checking (riscv-formal's discipline): prior art for what "an instruction retired correctly" observably means at a trace interface, applicable to the custom fragment as much as the base.

Discrepancies between anchors and RTL are results; choices the anchors leave open go to 02's register, not improvised here.

Obligations

1. The enumeration: every CSR address and instruction encoding the decode accepts beyond the ratified set, from the RTL, mechanically.
2. The generator-first draft of the custom fragment, the RTL diff, and the discrepancy log (each entry an S3-fidelity data point).
3. The Zihpm event table, extracted and stated.
4. The deviation log for the imported model — expected empty, checked not assumed.

Effort

Weeks, thinking-dominated — and less than a custom interrupt scheme would cost: the trap machinery, all three standard interrupts, and the debug register model are imported; what is left is an enumeration, a table, and however many custom control registers the enumeration finds. The fidelity risk is priced in axioms as S3 and cannot be engineered away, only anchored.

L4/02 — The choice register (S4)

Background

A standard written for many implementers cannot pin everything down, and does not want to. If the RISC-V spec dictated the reset value of every register, the handling of every misaligned access, and the priority of every simultaneous event, it would outlaw legitimate design choices and burden every implementation with someone else's decisions. So standards deliberately underspecify: "the contents of registers after reset are unspecified"; "a misaligned load may trap, or may be handled"; "pending interrupts are taken eventually." Each such sentence licenses a family of behaviours, and any member of the family is conformant. This is a feature — for implementers.

For a refinement proof it is a complication with a precise shape. Refinement (⊑) says every implementation behaviour is among the spec's allowed behaviours, so spec-side freedom is fine in principle — nondeterminism in the spec is exactly how "unspecified" is expressed formally. The problem is practical: a proof about this chip constantly needs to know which member of the family it is facing. When an L3 lemma about the trap handler needs to know whether a misaligned load traps, "the standard permits either" is not an answer the proof can use; the proof needs the answer for the generated core, and that answer is not derivable from the standard — only from the implementation and its configuration. It is a choice: a decision that narrows the standard's family down to the one behaviour this implementation exhibits.

Choices of this kind are epistemically different from theorems, and that difference is why they get their own register in the axiom ledger (S4). That the RTL agrees with a recorded choice is checkable — a lemma. That the choice itself is the right reading of the standard's freedom is not checkable by anything; it is legislative, like an editor resolving an ambiguity. The danger is not making choices — that is unavoidable — but making them invisibly: a proof that silently assumes registers reset to zero has narrowed the spec without anyone deciding to, and the narrowing is now load-bearing and unrecorded. Hence the discipline of this file: every choice is written down before it is used, with what the standard left open, what was picked, and which proof consumes it. (One instance of the pattern has a standard name worth knowing: WARL fields — "write any, read legal" — register bits where software may write anything and the hardware is free to read back any legal value, the standard's own idiom for per-field underspecification.)

Statement

Where RISC-V is deliberately underspecified, conformance is not a statement — the spec admits many behaviours, and a refinement proof needs one. This file is the register of choices: each entry picks a refinement of the standard, records that the pick is a choice, and becomes part of what ISA means. Deciding them before L3's proof starts is the discipline; discovering them mid-proof converts each into a stall.

The known entries

Rows marked elaborated carry values the generator itself declares (they appear in the emitted device tree); rows marked to record await the RTL extraction of the re-anchored configuration record.

The table is expected to grow; its shape is the point. Every entry has the same three fields: what the standard leaves open, what we fix, and where the fix is used. An entry whose third field is empty is a choice nobody needed — delete it rather than carry it.

One boundary to police as the rows get measured: this register only holds picks the standard's freedom licenses. If measurement ever shows behaviour the standard does not offer — a deviation rather than a choice — it lands in 01's deviation log instead, with its own evidence trail.

Two disciplines

Choices are S4-axioms, not theorems. "The choice is acceptable" is unfalsifiable in the same sense as S3's fidelity — the standard blesses the whole family, and picking is legislative. What is checkable: that the RTL agrees with the pick (an L3 lemma per entry, and for the measurable rows a configuration-record extension now), and that no lemma silently depends on an unrecorded pick (reviewable by grepping proofs for appeals to behaviour not derivable from Sail ⊕ S3 ⊕ this table).

Choices flow down, never up. A pick is made here and consumed by L3/L5; an L2 proof discovering it needs a behaviour fixed must stop and file the entry, not embed the assumption. The register is what makes "the spec" a single referent across three layers.

Relation to L5's clauses

L5's operating-conditions clause (out-of-envelope configuration → X-flood) and boundary decisions are the system-level analogue of this file — same S4 character, different layer's objects. Keep them separate: this register fixes meanings of architectural behaviours; L5's fixes the domain of the system claim.

Obligations

1. Measure the to record rows from the RTL (the re-anchored configuration record / layer checker) and pin them.
2. The per-entry agreement lemmas, handed to L3/10.
3. The grep-shaped audit: no proof appeals to un-registered behaviour.

Effort

Days to seed; the cost is the discipline, not the writing — and the payoff is that mid-proof stalls become filing operations.

L4/03 — Coverage: the encoding sweep and the cheap bulk

Background

A processor's decoder is not consulted only on the instructions the programmer meant to use. Every word that arrives from memory — a mistyped jump target landing in data, a corrupted image, a deliberately hostile input — goes through the same decode hardware, and the hardware will do something with it. An ISA therefore has to be a total specification: it must say what happens for all possible words, not just the meaningful ones. For the meaningless remainder the standard's answer is the illegal-instruction trap — the processor must recognise the word as invalid and transfer control to a handler, rather than executing whatever the decoder's don't-care logic happens to compute. A refinement claim that only covered the valid words would be false as stated: refinement quantifies over all executions, and executions containing garbage words exist.

This sounds like it demands 2³² proof obligations, and the reason it does not is worth understanding because it recurs everywhere in verification. The decoder does not treat words individually; it examines a few fields — the major opcode bits, the function-code bits — and the valid/invalid boundary is expressible as a modest set of regions of the encoding space, each region either matching one instruction's pattern or falling outside all of them. Checking a region is one query to a SAT solver ("does there exist a word in this region that decodes without raising the illegal flag?" — a question over a few dozen boolean variables, mechanical to answer). So the sweep is a few hundred solver queries, generated by a program, none requiring human thought.

That phrase — no human thought per case — is the point of this chapter's title. The project distinguishes obligations that are numerous but mechanical ("cheap bulk": generate, solve, count) from obligations that are few but deep (authoring the custom-extension spec, inventing the L3 invariant). Coverage is the model case of the first kind, and the chapter's closing advice is a useful heuristic for the whole book: the moment an individual coverage case starts to require judgment, it has been misfiled, and belongs with the thinking-dominated chapters instead.

Statement

The wide, shallow obligations that make ISA total over the instruction space: every encoding is either implemented (and matched to its Sail clause) or unimplemented (and proven to trap). Skip the second half and the refinement is simply false — a claim about all executions cannot ignore the words a program might contain.

The partition

From the configuration — rv32imac_zicsr_zifencei_zihpm_xrocket — the space partitions across two widths, because the C extension makes this a variable-length ISA:

implemented    RV32I base  ⊕  M (multiply/divide)  ⊕  A (atomics: lr/sc, amo*)
               ⊕  ALL of C (the 16-bit quadrants 00/01/10, minus reserved holes)
               ⊕  Zicsr (csrr* against the implemented CSR set, incl. machine-mode,
                  PMP, counters, and the xrocket custom CSRs)
               ⊕  Zifencei  ⊕  ecall / ebreak / mret / wfi
unimplemented  F/D (no floating point), supervisor-mode CSRs (no S-mode),
               reads of absent CSRs, reserved regions of both the 32-bit
               space and the 16-bit quadrants

Each implemented encoding gets the decode-equivalence + execute lemma pair (L3/10, templated by 00's addi/beq example). Each unimplemented encoding gets traps-correctly: the decoder raises the illegal-instruction exception and the machine takes the imported spec's trap step — mcause/mtval included, per the S4 rows. Two subtleties the sweep must partition alongside opcode space: a csrrw to an absent CSR is a legal instruction encoding whose execution traps — CSR address space is part of the sweep — and the 16-bit space's reserved holes (including the all-zeros word, defined illegal by the standard precisely because erased memory decodes to it) are regions of their own.

The measured half is an obligation, not yet a result. The spec side comes from the official riscv-opcodes tables at a pinned commit, so the patterns rest on the standard's own machine-readable encodings, not hand transcription. The implementation side — the decoder's own legality cubes, extracted from the generated RTL and compared exactly against the spec patterns — is the checker to re-run against this core (scoreboard). Decoders routinely accept a few reserved words via minimisation don't-cares, which is why the partition is designed three-way, with the third class a deliberate piece of spec design:

implemented   the spec patterns — matched to their Sail clauses
trapping      words the decoder REJECTS — proven to take the illegal-instruction
              trap step (a sweep against the measured rejected set)
spec-UB       any reserved words the decoder ACCEPTS — the spec assigns them
              UNSPECIFIED architectural behaviour; the measured set is
              expected small, and the clause survives any size

Spec UB, and why it is safe to say. For the UB class the ISA transition relation simply permits any successor architectural state (a demonic havoc step); refinement on those words is then trivial — which is exactly the point: the theorem deliberately claims nothing about them, instead of claiming something false. What makes this honest rather than a cop-out is the layering: UB at the ISA layer is still bounded by every layer below it. The invariant I still holds (the machine stays a coherent pipeline), the bus guarantees still hold (no malformed transaction), retirement still happens within the measure's bound, the electrical envelope is untouched — no instruction is a halt-and-catch-fire. This is the same move as L5/05's operating-conditions clause one level down: out-of-spec behaviour is not "anything may happen" but "anything may happen to the architectural state, within a machine that keeps functioning and can be re-anchored by trap or reset." The practical corollary: an execution that never fetches a UB word gets the full correspondence theorem — and for a fixed image, "contains no UB word" is a checkable property of F, to be enforced by an image checker over the partition once the decoder extraction lands. The checker earns its result by discriminating rather than by always agreeing — it must distinguish a UB word (accepted-reserved) from an unimplemented word (trapping), which is the distinction the three-way partition exists to make.

Why this is the model case of cheap entropy

The implemented patterns and the unimplemented complement: high raw spec entropy, zero invariant entropy — each obligation is one SAT-shaped query, independent of all others, because L3's interlocks cut every cross-instruction dependency at the register file. A lot of typing, almost no thinking; the thinking concentrated in S3 (01) and S4 (02). Most of L4 has this character, and the layer's effort estimate is dominated by it.

The sweep is also where encoding-space structure pays: the partition is decided by major opcode and format fields, so the unimplemented half is a small set of regions, not 2³² cases. The custom fragment adds CSR addresses (and possibly custom opcodes — 01's enumeration settles which), handled as further rows of the same sweep.

Obligations

1. Generate the partition — opcode regions across both widths and CSR addresses — from the configuration record; publish it as the single source both L3/10 and the compliance harness consume.
2. The decoder extraction and exact comparison against the spec patterns (the re-anchored checker; any accepted-reserved words land in the spec-UB class and the findings).
3. The traps-correctly sweep, mechanised (regions, not words).
4. The absent-CSR cases (F/D, S-mode, unimplemented counters) as explicit rows of the sweep.

Effort

Months of mechanised typing once L3/10's harness exists; near-zero marginal thought per encoding — by design, and worth preserving: any coverage case that starts requiring thought belongs in 01 or 02 instead.

L3 — RTL semantics = the microarchitecture

Node — RTL semantics, which is the microarchitecture: ⟦RTL⟧, the word-level transition system of the source text, defined for the synthesisable subset this design actually uses (00–04) and toured as the generated Rocket core it elaborates to (05–07). Used on both sides of the tower: L2's CEC compares against it, and this layer's own edge refines from it. Edge up — the ISA refinement (the genuine abstraction step): ⟦RTL⟧ ⊑ ISA, a stuttering simulation (I, α, m) — carried by the refinement statement (08), the invariant (09), and the per-instruction obligations (10). The node is a definition (its risk is inverted: a wrong definition yields a true theorem about the wrong object, so its obligations are well-definedness and adequacy, not proof); the edge up is the tower's one irreducible theorem — the ← THE WORK arrow no tool produces and no measurement substitutes for.

This layer is the merge of two: defining what the RTL means, and proving that what it means implements the ISA. They are the same object at two depths of description — a clean synchronous transition system, which when you look at what it computes is a five-stage pipeline. The node fixes the object; the edge up is the refinement.

Background

Before anything can be proved about the RTL, the RTL must mean something. Verilog's official semantics is an event-driven simulator with deliberately loose scheduling — unusable as a proof object — so the node defines the design's meaning directly, as a clean synchronous transition system, for exactly the subset of the language this design occupies, with membership mechanically checked rather than assumed (00, 01). The two conditions that make combinational logic actually combinational are checked in 02; the treatment of unknown values and reset in 03; and the question no proof can answer — whether the definition captures what the artifact really means — is made detectable, since it cannot be made provable, in 04.

That same transition system, read for its structure rather than its semantics, is the layer a computer-architecture course would recognise: a processor implementing its instruction set. The edge up proves exactly that, and it is the tower's irreducible theorem — the one piece no tool produces. The proof technique is the simulation: an abstraction function reads architectural state out of the hardware at commit points, an invariant describes the machine's in-flight state well enough to survive induction, and a measure bounds how long any instruction can take — all introduced from scratch in 08's Background, with the machine's anatomy toured in 05. The invariant (09) is where the thinking concentrates; the rest is wide, shallow, and largely mechanisable (10, 06–07).

The node: RTL semantics

A semantics for the synthesisable subset this design actually uses — not for Verilog: the simple synchronous semantics (two-phase non-blocking commit over an acyclic combinational pass), with the relationship to the LRM's event scheduler isolated as the scheduler-independence claim — probed by adequacy checks, stateable as a theorem. The subset is measured over the emitted design: one level-sensitive block (the clock-gate primitive), one X-idiom (23 memory-read don't-care sites), one initializer idiom, and the worst of the language's categories absent by construction.

Read structurally, that object is the generated Rocket core: a five-stage in-order pipeline with a 4 KiB instruction cache, a full bypass network, three ratified extensions (M, A, C), and standard machine-mode trap machinery, with its buses and debug port as assume-guarantee interfaces (05–07). Defining the object and touring the microarchitecture are the same act at two granularities — which is exactly why the old "RTL semantics" and "microarchitecture" layers are one node here.

The edge up: the ISA refinement

⟦RTL⟧ ⊑ ISA: a stuttering simulation (I, α, m) — invariant, abstraction read at retirement, measure — conditional on the bus contract (L5) and stated over the configuration record. Displayed in full in 08; inventing the invariant I is the one thing in the entire project no tool produces (09). ⊑ is trace refinement up to stuttering, not equality: the implementation takes many cycles per architectural step, so the obligation is a stuttering simulation with a measure function, not a cycle-accurate correspondence. This is the genuine abstraction step of the tower — unlike the horizontal CEC below it, which is an equivalence between two descriptions of the same machine.

Subcomponents

Interfaces

Consumes: the emitted SystemVerilog design cone (~230 modules) and its FIRRTL ancestor; the elaborated configuration record; the licence to reason discretely (L1); the bus contract and its latency bound B (L5); the Sail import including the machine-mode subset (L4). Exports: ⟦RTL⟧ to L2 (the CEC's right-hand side) and back to this layer's own edge; the configuration record to L4 (ISA subset) and L5; the reset/X story to L5's epoch model; and the refinement theorem — the tower's ← THE WORK arrow — plus the retirement-gap bounds (the measure read quantitatively, 08), consumed by L5/04's epilogue sizing.

Axioms introduced

None. The node is a definition (it once mirrored the netlist-semantics axiom S1, but S1 is now derived by the stack below; ⟦RTL⟧ has no such derivation, which is exactly why 04's checks matter — the failure mode is detected by the CEC cross-check and differential simulation rather than silent). The edge up introduces none of its own either; it is where the others are cashed in, its conditionality explicit: on B (L5), on S2/S3's spec fidelity (L4's ledger), on the configuration record, and on debug-inactive (05, 06).

The layer's shape

The node is the admissible-subset move plus its receipts. 01 fixes the boundary and proves the awful constructs absent; 00 gives the clean semantics that is correct for that subset — with scheduler independence as the honest statement of why the LRM can be ignored; 02 checks the two conditions without which the semantics is undefined; 03 reconciles the two-valued idealisation with physical power-up; 04 makes definitional error detectable. The node stays small because the subset is small — the target-selection decision, and the census is its receipt.

The edge up then rides on the machine's own structure. 05 fixes what is being verified; the pipeline's stage structure organises everything: retirement at WriteBack defines the commit points (08), the inter-stage register banks organise the invariant per stage (09), and the bypass/interlock discipline is precisely what restores the cross-instruction independence the per-instruction obligations need (10). The ports where the world enters are assume-guarantee pairs, the debug port quarantined behind a conditionality (06); the interrupt machinery is checked against the imported standard spec, with the small custom residue isolated (07).

Open problems

1. The invariant (09) — irreducible; the IC3 calibration decides how much of it is tedium vs. thought.
2. Prove scheduler independence for the subset (00) — bounded, genuine, severable from the critical path.
3. The fence.i / I-cache agreement story (05, 09) — small state, real content.
4. The register power-up story against the hardened netlist (03).
5. The residual authored semantics — the custom control CSRs (L4/01) — decide and record before proving.

First experiments

For the node:

• Extract and record the elaborated configuration (gates three other layers' scoping — cheapest high-value item in the layer).
• The completeness and RTL SCC checks (02) — an afternoon each, and both are hard failures the front end should enforce thereafter.
• The differential harness on the design's own testbenches (04).

For the edge up:

• Write the refinement statement and α before any proof (08) — against the core's own trace port (the retirement interface the ecosystem's co-simulation uses), checked on simulation traces as a cheap oracle.
• Extract the stall/flush/bypass structure from the emitted RTL and derive the retirement-gap bounds (05, 08).
• The IC3 calibration on the structural clauses (09) — cheap, and it sizes the layer's real cost.

Effort

3–6 months for the node — the smallest definitional piece in the tower, unusually well-bounded because the scope was measured rather than assumed; the only cost beyond the subcomponent sum is the elaborator front end, shared with X1's parser work. Then 1.5–3 years for the edge up: the pipeline, the bypass network, and three live extensions put this machine several rows up the effort-multiplier table from a multicycle core, but the mitigations are real — no data-cache miss machinery (the data side is a scratchpad), no speculation in this configuration, no virtual memory, no FPU, and a designer-declared trace port as a ready-made α anchor. The irreducible content remains plausibly a few hundred lines of clauses plus glue; the rest is the project-wide infrastructure item (symbolic simulation, bitvector automation, the stuttering framework).

Reading

Lööw's HOL4 Verilog semantics — the existing deep embedding, and the reference point for how much of the language one actually needs. The FIRRTL spec — the IR the design actually descends through, and the node's long-term anchor (04). The rocket-chip repository — the generator source is the design intent. Burch & Dill on flushing, and Manolios on WEB refinement — the two standard α constructions for pipelined machines. Sawada & Hunt on intermediate abstractions. Fox's ARM6 verification — a pipelined commercial ISA against a real microarchitecture, the closest existing analogue. riscv-formal's RVFI discipline — the retirement-interface prior art α should stay comparable with.

L3/00 — The elaborated object

Background

Hardware is designed by writing code. SystemVerilog, the language of this design's emitted RTL, is a hardware description language (HDL): a file that looks superficially like a C program but describes a circuit — its variables are wires and registers, and its statements describe logic that all exists, and all runs, simultaneously. The level of description is called RTL, register-transfer level: the design is expressed as a set of registers (state that updates on clock edges) plus the combinational logic computing, from current register values and inputs, what each register's next value will be. An RTL design has two essential statement forms. assign and always @* blocks describe combinational logic — outputs that are pure functions of current inputs, recomputed "instantly." always @(posedge clk) blocks describe clocked logic — assignments that take effect only at the clock edge, which is how registers are expressed.

The subtlety that makes Verilog semantics a research topic in its own right is what the language definition actually says these constructs mean. The official definition (the LRM — language reference manual) does not define a circuit; it defines a simulator: an event-driven scheduler that maintains a queue of value-change events and repeatedly picks one — in an order the standard deliberately leaves loose — and propagates it. Well-written synthesisable code is insensitive to that ordering; badly-written code is legal, simulates, and means different things under different conforming simulators. The one language mechanism to understand concretely is the two assignment operators: a blocking assignment (=) takes effect immediately, so later statements in the same block see the new value — sequential, program-like; a non-blocking assignment (<=) only schedules its update, and all scheduled updates commit together at the end of the time step. Non-blocking assignment in clocked blocks is what makes a bank of registers update simultaneously from the pre-edge values, the way physical flip-flops do — and it is why the discipline "clocked blocks use <=" is near-universal — and machine-kept here: the emitted design cone has no exceptions.

This chapter's task is to define what the RTL means for proof purposes: a function ⟦·⟧ assigning the design a transition system — a state set (the registers' values) and a step function (one clock cycle). The strategy is to skip the event-driven scheduler entirely and define the clean synchronous semantics a hardware designer has in mind anyway — evaluate all combinational logic, then commit all register updates at once — and separately establish (by check, and eventually by theorem) that for the disciplined subset this design lives in, the LRM's scheduler freedom cannot produce anything else. One more piece of jargon: elaboration — here it happens a storey earlier than in classic Verilog flows: the Chisel generator elaborates to FIRRTL, and the SystemVerilog arrives already parameter-free and unrolled, one module per elaborated instance shape. The semantics is taken of that already-elaborated design.

Statement

Define ⟦·⟧ : Config → RTL → TransitionSystem — the word-level transition system that is L2's right-hand side and L3's left-hand side. A definition, not a theorem; its correctness notion is adequacy (04).

The semantics, directly — not via the LRM

The Verilog LRM defines an event-driven scheduler with delta cycles and nondeterministic event ordering. We do not formalise it. ⟦·⟧ is defined as the simple synchronous semantics directly:

State  = declared regs (as bitvectors) ∪ memories
Input  = input ports
step   = 1. evaluate all combinational blocks/assigns to a fixpoint-free
            valuation (acyclic — [02](02-comb-blocks.md))
         2. evaluate every non-blocking RHS in the pre-state
         3. commit all non-blocking assignments simultaneously

Two-phase non-blocking commit is what makes always @(posedge) blocks order-independent among themselves; the acyclic combinational pass is W3's analogue one level up.

The implicit theorem this definition rides on — scheduler independence: for programs in 01's subset (non-blocking in clocked blocks, complete and acyclic combinational blocks, no delays/UDPs/triggers), every LRM-conformant scheduling computes exactly this semantics — the event-order nondeterminism is unobservable. This is what "semantically tame" formally means, and it is the content that 04's cross-checks probe empirically instead of proving: we define the clean semantics, and validate that the tools' LRM interpretations agree with it on this design. Proving scheduler independence for the subset would upgrade the adequacy story from tested to derived — a real (and bounded) formalisation target, but not on the critical path.

The two known deviations from "order doesn't matter" are exactly the flagged sites: the 2 clocked blocks using blocking = (order-dependent within the block — either model the intra-block sequencing explicitly or rewrite-and-prove-equivalent) and latch inference (02).

Word-level from the start

wire [31:0] is one declaration, so State is over bitvectors: SMT bitvector theory applies directly to L3's proof, arithmetic is +/* rather than carry chains, and the netlist-side structure of arithmetic is entirely L2/05's business (generic templates + trail). The word/bit boundary is crossed exactly once, at ρ (L2/03), and never inside this layer.

Configuration is part of the object

The generator is heavily parameterised — the whole SoC is a Scala configuration (core count, cache geometry, extensions, bus topology, peripherals) — and ⟦·⟧ takes the elaborated configuration as an argument. The emitted SystemVerilog arrives with parameters already resolved, so the configuration lives one storey up: the record extracted from the elaboration (the ISA string, the memory geometry, the device tree) determines which ISA subset L4 must cover and which structures L3's tour prices. Recording it exactly is a deliverable, not bookkeeping, and re-running the elaboration from the pinned generator is the check that the record describes the design rather than one build.

Obligations

1. Write the semantics for the subset (small — the step function above plus expression evaluation over bitvectors).
2. Extract and record the elaborated configuration from the generator run.
3. State scheduler independence precisely, even if its proof is deferred — the statement is the layer's honesty about what the LRM relationship is.

Interface (down to L2). The S-frontend seam is the still-open factor of L2's l2_commutes: that the Yosys front-end (proc/techmap/flatten) producing the synthesis trail's head s0 from this ⟦RTL⟧ preserves the cone functions. The trail s0 → … → N is certificate-checked pass by pass; this first hop, from the elaborated object to the trail head, is not — the last trusted step inside an otherwise-proved equivalence.

Effort

Weeks for the definition; the deferred scheduler-independence proof is the only open-ended item and is severable.

L3/01 — The subset, measured

Background

Verilog (and its superset SystemVerilog) is really two languages sharing a syntax. One is for describing hardware; the other is for writing testbenches — simulation-only code that pokes the design with stimuli, and may freely use constructs with no physical counterpart: #10 ("wait ten simulated nanoseconds"), force (reach in and override a wire), fork (spawn parallel processes), DPI calls into C. Synthesis tools accept only the first language — the synthesisable subset — and even that subset has dark corners the standard leaves loose: casex's treatment of unknown values is a famous source of simulation/synthesis mismatch, and an explicit 'bx literal drags the simulator's "unknown" value into design semantics. A formal semantics for all of the language would be enormous, contested, and mostly spent on constructs that describe no hardware.

The move this chapter makes — the same one the book makes at every layer where a messy industrial format appears — is to refuse the general problem. Instead: choose a well-behaved subset, give the semantics for exactly that subset, and mechanically check that the design lies inside it, so that every dark corner becomes a parse error rather than a semantic question. Nobody has to formalise what force means if a checker proves force never occurs. What makes this cheap here is that the RTL is compiler output: the SystemVerilog is emitted by CIRCT's firtool from FIRRTL, and a compiler back end emits a small, rigid idiom — the same handful of construct shapes, thousands of times.

Statement

A semantics for the synthesisable subset this design actually uses — not for SystemVerilog. The target source is the emitted design cone: ~230 modules of machine-generated SystemVerilog (80 K lines across the emitted collateral, which also carries the simulation harness — excluded from the cone by the synthesis file list). The census, measured over the emitted files:

The numbers say something structural: a compiler back end has already done the subset-discipline work. There is exactly one level-sensitive block in the entire design, one X-idiom, one initializer idiom — because one code generator emitted everything. The dark-corner constructs are not rare; they are absent, and absent by construction rather than by an author's care.

The admissible-subset move, third instance

This is the same manoeuvre as L1/00 (GDS: forbid pathtype 1, self-intersection, non-90° SREF) and L2/00 (structural Verilog: ~20 productions): define the semantics for a well-formed subset chosen to match what production artifacts actually contain, and check membership rather than assuming it. The subset boundary is enforced by the front end — a construct outside it is a rejection, not a guess. The pattern's value is that the semantics' hard cases become parse errors: nobody has to decide what force means because the checker proves it never occurs.

The discipline that follows: write the semantics for exactly what appears. Every construct in the subset gets its meaning from 00's simple semantics; every construct outside it is rejected; there is no third category of "handled approximately."

The generated-source situation

The target source is machine-emitted, and — unlike most generated RTL — its generator has a written-down input semantics: the design exists as FIRRTL, an intermediate representation with a specification, before firtool lowers it to SystemVerilog. The consequences cut both ways. Per construct, the emitted code is easier than hand-written RTL: one idiom per construct class, no dark corners, no author styles. Per meaning, the SystemVerilog is the output of a compiler nobody has verified — so the layer carries two anchors instead of one: the emitted-subset semantics defined here, and the FIRRTL-level semantics one storey up, with the lowering between them as a checkable seam (04). That second anchor is what a hand-written design can never have.

Obligations

1. Re-run the census as an enforced boundary over the synthesis file list (the design cone, mechanically separated from the harness collateral); pin it as a regression — a construct appearing after a generator bump must fail loudly.
2. Freeze the subset grammar as the front end's acceptance language.
3. The clock-gate wrapper's primitive contract (02) — the one construct that is not combinational-or-clocked.

Effort

Days — the census is measured; the work is promoting it from measurement to enforced boundary.

L3/02 — Combinational blocks: completeness and acyclicity

Background

Combinational logic — the half of RTL that computes rather than remembers — is only combinational if two conditions hold, and Verilog enforces neither. This chapter is about checking them, and the failure modes are worth seeing concretely because both are classic ways real designs go wrong.

The first condition is completeness. An always @* block is meant to describe a pure function: for any inputs, compute the outputs. But consider a block that assigns out inside if (sel) out = a; and forgets the else. When sel is low, the block assigns nothing — and Verilog's semantics says out then keeps its previous value. Keeping a previous value is memory: the "combinational" block now describes a storage element, and synthesis tools dutifully build one — a latch (a level-sensitive storage element, transparent while its enable is high, as opposed to the edge-triggered flip-flops of clocked logic). This "latch inference" is silent, legal, and changes the circuit's state space: a state element exists in the netlist that the RTL's author never intended, no reset touches, and no proof about the intended design accounts for. The fix is a per-block check that every control path assigns every output — mechanical, and worth its weight in gold.

The second condition is acyclicity. Combinational blocks read each other's outputs, and if the read-dependency graph contains a cycle — block A computes x from y while block B computes y from x — there is no well-defined order to evaluate them in, and "evaluate all combinational logic" stops being a definition. (In physical hardware the same cycle is a feedback loop that may oscillate or settle unpredictably; the netlist-level version of this check is L2's W3.) The check is a standard graph computation: build the dependency graph, find its strongly connected components (maximal sets of nodes mutually reachable from each other — the canonical algorithm is Tarjan's, linear time), and demand every component be a single node. The one wrinkle at RTL level is apparent cycles that never realise because the two directions occur on disjoint control paths — where the honest options are a conservative syntactic rejection or a finer per-path analysis, and conservatism wins unless it actually fails.

Statement

The two well-formedness conditions on the combinational sublanguage, without which 00's step function is not defined. These are W1–W4's analogues one level up, and one of them is the single most consequential check in the layer.

Completeness: one level-sensitive block, by design

An always @* block that fails to assign an output on some control path makes that output hold its previous value on that path — the language silently infers a latch, and the block is no longer combinational. The formal condition:

∀ block B, ∀ output v of B, ∀ control path π through B:   π assigns v

The emitted design makes this almost a non-event: the compiler expresses combinational logic as assign expressions, so the design cone contains exactly one always @* block — and it is a latch on purpose. EICG_wrapper, the integrated-clock-gate model, latches its enable while the clock is low (if (!in) en_latched = en || test_en) and gates the clock with the latched enable — the textbook glitch-free clock gate, mapped to a dedicated clock-gate library cell in hardening. The right treatment is not to "fix" the incomplete block but to remove it from the combinational sublanguage entirely: the wrapper is a primitive with its own contract (enable sampled while the clock is low; the gated clock equals clk ∧ en_latched), consumed by L1's clock analysis. The completeness check then quantifies over the remaining blocks — expected to pass vacuously — and its standing job is to catch any unintended latch a future generator bump might introduce, the failure that changes the circuit: a phantom state element appears, ρ (L2/03) has no RTL counterpart for it, and the refinement is false, not merely harder.

Acyclicity: the RTL-level W3

Combinational blocks and assigns read each other's outputs; the read-depends-on graph must be acyclic for the fixpoint-free valuation to exist. Verilog permits combinational loops (the language would give simulation nontermination or oscillation; hardware would give L3/W3 violations). The check is the same SCC computation as W3, over RTL signal dependencies instead of nets — to be re-run over the emitted cone by the layer's checker (yosys's scc pass), with zero SCCs the expected verdict for compiler-emitted code and any hit a generator finding.

The same elaboration answers a third question for free — wires that are read but never driven, which are X sources. Most such reports are artifacts of reading a module whose drivers live in an absent macro (here, the SRAM macros), so the discriminator is whether the unit under check is a closed hierarchy; the sweep must therefore run with the macro behavioural models in place, and any genuinely undriven wire is a finding whose harmlessness must be established, never assumed.

One subtlety absent at netlist level: apparent cycles through a block that never realise (block A reads x, writes y; block B reads y, writes x; but on disjoint control paths). The netlist after synthesis resolves this through mux structure; at RTL the honest options are the conservative syntactic check (reject apparent cycles — likely sufficient here) or a per-path refinement. Take the conservative check unless it fails.

The blocking-assignment residue

There is none in the design cone: the emitted clocked blocks are uniformly non-blocking (the census's four blocking sites are DPI harness collateral outside the cone). 00's two-phase semantics therefore applies without a normal-form rewrite — one whole class of order-dependence obligations deleted by the compiler's discipline.

Obligations

1. The completeness check over the cone's blocks, as a front-end hard failure (shared with L2's naive-netlist well-definedness), with the clock-gate wrapper carved out as a primitive.
2. The RTL-level SCC check, conservative version.
3. The clock-gate primitive contract, stated once and exported to L1.

Effort

Days. Small, sharp, and everything downstream assumes it silently — which is precisely why it gets its own file.

L3/03 — X and initialisation

Background

When a chip powers up, its flip-flops hold arbitrary values — physically, whichever way each bistable circuit happened to tip as the supply ramped. Hardware practice represents this ignorance with a third logic value, X, meaning "unknown: could be 0, could be 1." A freshly powered design is all-X, and a reset sequence exists precisely to fight X: registers with a reset connection get driven to definite values, and definiteness then propagates as the machine runs. But not every register has a reset connection — adding one costs area and wiring, so designers deliberately leave uninitialised any register whose value provably doesn't matter until first written (a register file is the classic case: garbage in a register you haven't written yet is harmless, because reading it was never meaningful). The result is that a real design's early life is a mixed X-and-definite state, converging toward definiteness at a rate the designer controlled by choosing which resets to pay for.

Reasoning about this uses ternary simulation (industrially, "X-propagation" or X-prop analysis): run the design's logic over the three-valued domain {0, 1, X}, where each gate maps unknown inputs to unknown outputs except where a known input forces the answer (0 AND X = 0 — the X never mattered). A ternary run of the reset sequence starting from all-X computes, conservatively, exactly which bits are guaranteed definite afterward — and because it starts from all-X, its conclusion holds from arbitrary pre-reset garbage, which is what lets one proof serve power-on, brown-out recovery, and post-upset reset alike.

The chapter's actual subject is a mismatch this creates. The semantics defined in 00 is two-valued — every register always holds a definite bitvector — because two-valued semantics is vastly more tractable for the refinement proof above. That is a strengthening of reality, and unjustified strengthenings are how proofs come to be about the wrong machine. The resolution below splits the gap three ways — prove X is eliminated where the spec claims definiteness, match X against the spec's own reset nondeterminism where the standard itself says "unspecified," and prove the residue never influences anything observable — with the second arm being the elegant one: the ISA's deliberate underspecification (choice C1 in L4/02) turns out to be exactly shaped to absorb the hardware's uninitialised registers.

Statement

⟦RTL⟧ as defined is two-valued — every register holds a definite bitvector — which is a strengthening of reality: power-up state is all-X (L1/03's value lattice), and real cores deliberately leave registers unset. The obligation is to justify the strengthening exactly where it is used and refine it where it is not justifiable.

The resolution, in three parts

Where the spec claims definiteness, prove X-elimination. pc, the FSM state, and reset-defined CSRs must be definite after reset. The obligation: the reset sequence, run in ternary semantics from the all-X state, drives these bits definite. This is checkable by ternary symbolic simulation (industrial "X-prop" verification), and its quantification over the all-X start state means it covers arbitrary pre-reset garbage — so brown-out recovery and SEU-recovery reset ride on the same proof (L5's epoch model consumes exactly this).

Where the spec permits nondeterminism, refine into it. RISC-V leaves general registers unspecified at reset. Implementation-X on those bits is not eliminated but matched: the refinement maps untracked implementation state into the spec's own reset nondeterminism. The register file simply never needs an X-elimination argument — a large saving discovered by aligning the obligation with what the spec actually claims.

Where neither applies, prove value-independence. Any remaining uninitialised bit must never flow to an observation before being written. In ternary terms: X from that bit never reaches a definite-claimed output. These are the classical value-independence lemmas, now stated as X-flow properties — per-bit, mechanical, and expected few after the first two parts have consumed the bulk.

The initial blocks and the X idioms

The census found 212 initial blocks — overwhelmingly one machine idiom, the compiler's register-randomization initializer, whose entire body sits behind simulation-only macro guards. With those macros undefined (every synthesis run), the blocks are empty: no register in the design carries a power-up value, which is exactly the all-X starting point this chapter's ternary story wants, stated by the emitter itself. The idiom exists so that simulation can start from randomized rather than zeroed state — the ecosystem's own defence against code that accidentally relies on uninitialised registers reading zero, i.e. a fuzzer for precisely this chapter's third obligation.

The design's 23 'bx literals are also one idiom: behavioural memory models yield X on a read with the enable low (read_data = en ? mem[addr] : 'bx). Per site, that is a declared don't-care — the generator asserting that disabled-read data is never consumed — which converts directly into a value-independence obligation: X from a disabled read never reaches a definite-claimed output. (In the hardened netlist these models are replaced by SRAM macros whose disabled-read behaviour is the macro contract's business — the RTL X-site and the macro contract must agree, a small cross-layer check.)

Interfaces

This file is where three layers meet, deliberately thin: L1/03 supplies the value lattice and the claim that reset is an X-elimination event; L2/03's ρ requires the reset-state correspondence this file establishes; L5's epoch model consumes "X-elimination from arbitrary state" as its per-epoch base case. The proof lives once, here.

Obligations

1. The ternary reset simulation for the definite-claimed set (pc, FSM, CSRs).
2. The spec-nondeterminism matching clause in the refinement statement (with L3/L4: which architectural state is reset-unspecified).
3. The residual value-independence sweep.
4. The disabled-read value-independence sweep over the 23 memory X-sites, and its agreement with the SRAM macro contracts.

Effort

Weeks, mostly tooling for the ternary simulation; the conceptual work was done when the obligation was split three ways.

L3/04 — Adequacy: how a definition can be wrong

Background

Theorems are checked by proof; definitions are checked by nothing. When 00 defines what the SystemVerilog means, no downstream proof can catch an error in the definition itself — if the semantics says an operator does the wrong thing, every theorem built on it remains perfectly valid about the wrong machine, and the proof assistant will never complain. This is the deepest kind of gap in any formal verification project: it lives in the correspondence between a mathematical object and the informal thing it claims to formalise, where proof cannot reach. The property wanted is called adequacy — that the formal semantics faithfully captures what the artifact actually means — and since it cannot be proved, the engineering question becomes: how do you make inadequacy detectable?

The general answer is triangulation against independent interpretations, and its cheapest instrument is differential testing: run the same design under your semantics and under independently-written simulators, on the same inputs, and compare outputs cycle by cycle. Any disagreement pinpoints a construct whose meaning is contested. The method's power comes from independence and its weakness is coverage: it only tests behaviours the test inputs exercise. This design adds a structural instrument most projects lack: the RTL is not the top of its own derivation. It is compiler output — the design exists first as FIRRTL, an intermediate representation with a written specification, and CIRCT's firtool lowers it to the SystemVerilog the flow consumes. A specified IR one storey above the RTL means the semantics can be cross-anchored: define the meaning of the emitted subset, define (or import) the meaning of the FIRRTL, and check that firtool's lowering relates them. Disagreement at any triangle edge is a detection.

Statement

⟦·⟧ is a definition, so nothing downstream can prove it right — a wrong semantics yields a true theorem about the wrong object, and no checker catches it. Adequacy is established by making disagreement with independent interpretations detectable, four ways with different coverage.

The four checks

Differential simulation. Elaborate under ⟦·⟧, run the ecosystem's own test programs, compare cycle-by-cycle against Verilator (the framework's native simulation path) and a second independent simulator. Cheap, catches the crude failure modes (wrong operator semantics, wrong commit order), coverage limited to what the tests exercise — and this design ships an unusual asset here: thousands of generator-emitted assertions (the TileLink monitors alone are 85 files of them), which run inside the differential harness as behaviour probes written by the design's own authors.

The CEC cross-check — the strong one. L2's equivalence compares ⟦RTL⟧ against a netlist produced by Yosys's interpretation of the same source. If our semantics differs from Yosys's anywhere the design's logic depends on, the CEC fails — the mismatch surfaces as a cone that won't prove, pointing at the construct responsible. Two independent implementations of the subset agreeing on a 50-thousand-cell design is real evidence, and crucially the failure mode is detection, not silence. This converts the scariest definitional risk in the top-down architecture into checked-on-this-instance.

The IR anchor — the structural one. The FIRRTL file the design passes through has a specification independent of any simulator, and the elaboration that produced it is deterministic and re-runnable from the pinned generator. Two uses, increasing in strength. Today: re-elaboration — regenerate the FIRRTL and the SystemVerilog from the pinned sources and diff, which separates properties of the design from properties of one build. Eventually: a semantics for the FIRRTL subset the design occupies, with the lowering checked — at which point L3's SystemVerilog semantics stops being load-bearing and becomes a checked artifact of the flow, the "shrink to nearly nothing" this layer's architecture aims at. The obligation between here and there is honest: firtool is a large unverified compiler, and until the lowering is checked per-design (CEC between FIRRTL semantics and emitted-SV semantics), the IR anchor detects drift without certifying the lowering.

Scheduler independence, if proved (00) would upgrade the story from "agrees with two schedulers on this design" to "agrees with every LRM-conformant scheduler on every program in the subset." Bounded, genuine, deferred.

Honest limit shared by the first two: coverage is this design's constructs and behaviours. That is exactly the right scope for a validation project — the semantics needs to be right about the generated core, not about SystemVerilog — and the subset boundary (01) is what makes "right about this design" a closed question rather than an open-ended one.

Why this layer is small here

The classic version of this chapter, for a hand-written design, carries the whole weight of "what does this Verilog mean" with only simulators to triangulate against. Here the design descends through a specified IR emitted by a disciplined compiler: the subset is one generator's idiom (01), the dark corners are absent by construction, and the IR gives the semantics a second, independent anchor with a specification document. The layer's long-term shape is exactly the IR route: put the semantic weight on FIRRTL, check the lowering per design, and let the SystemVerilog semantics be the small, checked bridge it deserves to be. That is also where the project's certification endgame naturally lands — a lowering that emits an equivalence certificate per module would discharge this layer's residue as a by-product.

Obligations

1. The differential harness (elaborate, run, compare — days), with the emitted assertion collateral enabled.
2. Wire semantics-mismatch triage into L2's CEC failure reporting, so a non-proving cone distinguishes "synthesis did something" from "our semantics disagrees with Yosys."
3. The re-elaboration check: regenerate FIRRTL + SystemVerilog from the pinned generator and diff against the artifacts of record.
4. (Deferred) scheduler independence for the subset; the FIRRTL-subset semantics and the per-design lowering check.

Effort

Weeks for the harness; the cross-check comes free with L2. This file is small because the strategy is to inherit adequacy evidence from work other layers do anyway — which is the correct shape for a definition layer.

L3/05 — What the microarchitecture actually is

Background

The ISA says what the processor does; the microarchitecture is how — the actual arrangement of registers, adders, multiplexers, and control logic that carries each instruction out. The distinction is the deepest one in computer architecture: dozens of wildly different microarchitectures implement the same ISA, from a chip executing one instruction over several clock cycles to a server core juggling hundreds at once, and software cannot tell them apart except by speed. This chapter is the guided tour of the core's microarchitecture, and since the tour uses the standard vocabulary of a computer-architecture course, here is the minimum of it.

The core is pipelined: instead of finishing one instruction before starting the next, the machine is an assembly line of stages, each doing one phase of the work — fetch the instruction, decode it, execute the arithmetic, access memory, write the result back — with several instructions in flight at once, one per stage. The price of the overlap is hazards: instruction B may need a register value that instruction A, two stages ahead, has computed but not yet written back. The two standard remedies are interlocks (stall B until A's result lands — simple, slow) and forwarding/bypassing (route A's result sideways into B's stage — fast, more wiring and more invariant); this machine has a full bypass network, so the forwarding-correctness clause family is part of the price of realism here. Branches add a second complication: by the time a branch's direction is known, younger instructions have already entered the pipe on the fall-through path and must be flushed — squashed as if they never happened — which is why serious cores add branch prediction, and why its absence in this configuration matters. A cache is the third piece: a small on-chip memory holding recently-used contents of a larger, slower one, consulted first on every access — here an instruction cache on the fetch side, while the data side is a tightly-integrated memory (a scratchpad at a fixed address) rather than a cache, which deletes the entire miss/refill/writeback machinery from the data path.

Everything else on the big-core menu is absent — no data cache, no store buffer, no out-of-order execution, no MMU, no floating point — and the presence/absence table below prices each item either way.

Statement

The concrete anatomy of the generated core — Rocket in the framework's tiny configuration, as declared by the elaboration (the device tree carries the headline numbers) and to be re-measured from the emitted RTL by the layer's checker. The tour is organised as the standard computer-architecture walk, with each present structure priced alongside each absence. Facts marked to record await the re-anchored configuration record.

The pipeline

Rocket's classic five stages:

Fetch (icache, RVC expansion) → Decode → Execute (ALU, branch) → Memory (DTIM, atomics) → WriteBack

Roughly five instructions in flight, with bypass paths routing results backwards from Execute/Memory/WriteBack into younger instructions' operand reads. The control bundle rides the pipe with each instruction, so the invariant's "decode coherence" clause becomes a per-stage family: what each stage's control bits must say about the instruction they travel with.

The tour

Fetch and the I-cache. A 4 KiB, direct-mapped instruction cache (64 sets × 64-byte blocks — the elaboration's own numbers), read and hit-checked in the front end, with a miss triggering a TileLink refill burst. Because the C extension is implemented, fetch groups are 16-bit aligned and an RVC expander rewrites compressed instructions to their 32-bit forms before decode — an extra function to verify, with the standard's own expansion table as its spec. The cache brings the fence.i obligation — the ISA's synchronise-instruction-stream operation: stores land in the DTIM immediately, but the I-cache can hold stale code until flushed.

Decode. A generated decoder (elaborated from the instruction table in the generator source) producing the control bundle. Exhaustiveness/exclusivity obligations attach to the decoder function itself, per L4's coverage sweep.

Hazards. Full bypassing with interlocks where bypassing cannot help (load-use, mul/div in flight, CSR side effects) — so the invariant carries both clause families: forwarding-correctness ("the value routed sideways equals the value that will be written back") and stall-correctness ("no reader advances past an unresolvable writer").

Execute. ALU and address generation; branch resolution with no predictor in this configuration (to record: the tiny config elides the branch-target buffer) — a taken branch flushes the younger pipeline contents, the flush a spec-visible stutter burst, "flushed instructions have no architectural effect" an invariant clause with real content. The multiply/divide unit is iterative (small-configuration parameters — to record), a classic loop-invariant obligation.

Memory. The data side is the 16 KiB DTIM — a scratchpad, not a cache: fixed address window, no tags, no misses, near-single-cycle. The A extension lives here: an atomic ALU performs the amo* read-modify-writes at the memory, and an LR/SC reservation tracks the conditional pair (its granularity and progress conditions are S4 rows — L4/02's C7).

WriteBack. The register-file write and the retirement point — the natural commit point for α. Rocket exposes a designer-declared instruction trace port (the retirement interface the ecosystem's co-simulation uses), which is the α anchor: architectural effects are read where the design itself says instructions retire.

CSRs and interrupts. The CSR file implements the standard machine-and-user-mode subset: the trap/interrupt CSRs (mstatus/mie/mip/mtvec/mepc/mcause/mtval/mscratch), the counters (Zihpm), PMP (8 regions, granularity 4), and the custom xrocket control CSRs (L4/01's enumeration). All three standard interrupt lines are live — software and timer from the CLINT, external from the PLIC — so the trap machinery is imported spec end to end, with the custom CSRs as the only authored residue. The reset vector is a constant (the boot ROM base).

The debug module. The standard RISC-V debug architecture, reached over JTAG: halt, step, abstract commands, out-of-band access to architectural state. The refinement must be stated conditional on debug-inactive (the same move as scan chains in L2/05's contingency table), with the debug session itself specced separately via the debug spec's own register model.

The presence/absence table — both directions priced

The configuration sits deliberately in the middle of the ladder: a real pipeline with real bypassing and three ratified extensions, but with the data-side miss machinery, speculation, and virtual memory all absent — each absence a clause family the proof never pays for.

Obligations

1. The stall/flush/bypass structure and per-instruction pipeline-occupancy bounds, extracted from the emitted RTL (the re-anchored stage-graph checker).
2. The retirement/α story instantiated for this pipe (08) and the invariant's per-stage clause sketch (09).
3. The I-cache agreement invariant and the fence.i obligation, stated.
4. The debug-inactive conditionality, stated once and threaded.
5. The to record rows (BTB absence, mul/div parameters) pinned by measurement.

Effort

Days — descriptive, measured from source. What it feeds — the invariant and the per-instruction sweep — is priced in the layer README.

Reading

The rocket-chip generator source — the Scala is the design intent the generated SystemVerilog implements. Burch & Dill and Manolios (WEB) for the α constructions. Hennessy & Patterson for the pipeline/hazard/cache vocabulary at textbook depth.

L3/06 — The buses and the debug module

Node: this file is the object — the tile's TileLink ports and the debug module as structure. The request-discipline guarantees the core proves (the interface half of the refinement edge) are the edge, 11.

Background

This chapter proves the core's half of the bargains struck at its external ports. The general story — what a bus is, why memory latency varies, and how assume-guarantee reasoning splits an interface proof into promises proved by each side separately — is introduced in L5/02's background, worth reading first; L5 authors the fabric's promises to the core, and here the core proves its own request discipline in return.

The protocol at the tile's ports is TileLink: requests on the A channel (opcode, address, size, source ID), responses on the D channel tagged with the matching source ID, valid/ready handshakes per beat, multi-beat bursts for transfers wider than the bus. The fetch side issues cache-line refill bursts — a line-aligned read streamed over consecutive beats; the data side issues the accesses the DTIM and the memory map serve, including the A extension's atomic operations, which TileLink carries as first-class opcodes rather than as read-modify-write sequences improvised by the master.

One more port exists that most tours omit: the debug module, through which an external agent over JTAG can halt the core, single-step it, and run abstract commands — reaching architectural state without going through the program. For refinement purposes it is a side door, and the standard treatment is the one L2/05 gives scan chains: state the theorem conditional on the door staying shut, and spec the door separately via the RISC-V debug specification's own register model when it is used.

Statement

The tile's TileLink masters and the debug module, as contracts: what the core guarantees about its requests (proved here), what it assumes about responses (L5's contract, with its latency bound B), and the debug-inactive conditionality stated once.

The instruction port

The I-cache's refill master. Its request-discipline guarantees — Gi1–Gi3, provable as invariant clauses (09 clause 7) — are stated with the other obligations in 11. Assumed in return: the D-beat within B per beat, data valid at the beat, boot-region reads return F's contents (L5's A4, with the split between bridge-proved and far-agent-assumed marked there).

The data port

The data-side master; its guarantees Gd1–Gd4 are stated in 11, and the assumed half mirrors the instruction port's.

The debug module

The standard debug architecture: a debug module on the peripheral bus, driven by a debug transport module that terminates the JTAG pins, with halt-request/resume/abstract-command machinery reaching the core. Two facts shape the treatment. First, the module's register model is imported — the RISC-V debug specification defines dmcontrol, abstractcs, and friends — so unlike a bespoke debug unit there is a document to be faithful to rather than semantics to author. Second, the module is also a bus master: system-bus access lets the external agent read and write memory directly, which is one of the load paths for F (L5/03). The refinement is stated conditional on debug-inactive (no halt request in flight, no abstract command executing); the conditionality is one hypothesis, threaded once through 08's statement. The hardware-side obligation that discharges it — inactive means invisible — is the non-interference lemma stated in 11.

What the absences buy

No coherence protocol in flight (the tiny configuration's bus topology is incoherent by construction), no store buffer, no miss queues beyond the single refill: the memory system is a small set of masters with static discipline, and the whole arch-class topic "memory hierarchy" reduces to the contracts above plus one latency bound. The counterfactual — caches with miss queues, store buffers with forwarding, a coherence protocol — is priced in 05's table; this file is the demonstration that the generated machine stays on the cheap side of it.

Effort

Days; the structural description is small — the two masters and the debug side door as objects, plus what their absences buy. The proof weight is in the guarantee clauses and the non-interference lemma, which are the edge, 11.

L3/07 — Traps and interrupts

Node: this file is the object — the trap/interrupt mechanism (the imported machine-mode machinery, the interrupt sources, the synchronous surface). The proof that it refines the machine-mode ISA is the edge, 12.

Background

An interrupt is the mechanism by which the outside world interrupts a running program: a device raises a wire, and the processor — at a suitable boundary — suspends the program, saves enough state to resume it, and jumps to a handler. RISC-V specifies this machinery in its privileged architecture: on a trap (an interrupt, or a synchronous exception like an illegal instruction), the machine saves the interrupted pc to mepc, records the reason in mcause, stacks the interrupt-enable bit inside mstatus, and jumps to the handler address in mtvec; the handler returns with mret, which unstacks and resumes. Interrupt delivery is governed by two CSRs — mip (which interrupts are pending) and mie (which are enabled) — gated by the global enable bit mstatus.MIE. The core implements exactly this machine-mode machinery, so the specification is imported — the Sail privileged subset, ratified standard — not authored.

The system side is the standard shape as well, which is worth appreciating as a cost that didn't materialise: all three standard interrupt lines are live. The CLINT drives the software-interrupt and timer-interrupt pending bits (msip from its software-interrupt register, mtip from the mtime/mtimecmp compare), and the PLIC drives the external-interrupt bit, funnelling its device sources (the UART) through gateways, priorities, and a claim/complete protocol. Both devices sit behind the memory map, so their register semantics are device models — L5/03's business — while the core-side delivery machinery is entirely the imported spec. What remains authored at the core is only the custom control CSRs (L4/01), and their spec must say they never alter delivery semantics.

The synchronous side is the standard's full surface: illegal instruction, misaligned load/store, access faults (a denied TileLink response does arrive as a precise access-fault trap — the error device makes even unmapped addresses well-behaved, L5/03), breakpoint, and the environment calls. The exact per-cause behaviour is the choice register's to record (L4/02); this chapter's lemmas consume it.

The proof that this machinery refines the machine-mode spec — the six proof obligations, the anchors against spec-side error, and the delivery split — is the edge this mechanism carries, 12.

Effort

Short; the mechanism is imported standard machinery — the Sail privileged subset plus standard interrupt sources. The refinement proof and its cost (mostly standard months, with the S3 residue) are the edge, 12.

L3/08 — The refinement statement

Background

How do you prove that one machine correctly implements another? The two machines don't even step at the same rate: the ISA executes one instruction per step, while the hardware spreads each instruction across pipeline stages, retiring one per cycle at best and pausing for stalls, cache misses, and flushes — with the in-flight remainder corresponding to no ISA state at all. The technique that bridges this — the central proof technique of the entire book, used here at full strength — is the simulation proof, best understood as a picture before formulas. Here it is, for a run in which one instruction retires, the pipe then stalls twice (an interlock, then a cache miss), and a second instruction retires:

ISA  ····▶ A ────step────▶ B ······························▶ B ────step────▶ C ▶ ····
           ▲               ▲                                 ▲               ▲
         α │             α │                               α │             α │
RTL  ····▶ s₀ ──cycle───▶ s₁ ──cycle───▶ s₂ ──cycle───▶    s₃ ──cycle───▶  s₄ ▶ ····
           (retire)        (stall)       (miss refill)      (bubble)        (retire)

The struts are the abstraction function α, which reads the architectural state (register file, program counter, CSRs) out of a hardware state at the retirement boundaries — the cycles where the WriteBack stage completes an instruction and the machine's committed state is architecturally clean. Between retirements the hardware is mid-flight everywhere at once; those cycles are stutters, and they are characterised not by α but by the invariant I — the description of the reachable in-flight states, 09's subject and the layer's real work — together with the measure m, a counter that strictly decreases across every stutter and thereby forces the next retirement within bounded time. (Without it, a machine could stall forever, implementing nothing while never being caught.) The trailing arrows continue the ladder in both directions. The proof obligation is local, one cell at a time; induction tiles the cells into the global statement: every run of the hardware, viewed through α, is a legal run of the spec. A global claim about infinite behaviours is bought with finite, checkable, per-cell facts — that trade is the whole magic of the method.

Statement

⟦RTL⟧ ⊑ ISA: a stuttering simulation whose shape is fixed now, even though its invariant is future work —

∃ I ⊆ States(⟦RTL⟧)          the invariant                    [02]
∃ α : I → States(ISA)         abstraction, read at retirement
∃ m : I → ℕ                   the measure

init:  reset states ⊆ I   ∧   α maps them into ISA reset states
                              (X ⊑ spec reset nondeterminism — L3/03)
step:  s ∈ I, s →_rtl s'  ⟹  s' ∈ I  ∧
         either  α(s') = α(s)  ∧  m(s') < m(s)        (stutter)
         or      α(s) →_isa α(s')                     (retire / trap / interrupt)

conditional on the bus contract (authored in L5, assumed here), on debug-inactive (06), and stated over the configuration record (L3).

Commit points, α's domain, and the trace port

Retirement is where the pipeline is architecturally honest: when WriteBack completes an instruction, the register file, CSRs, and committed pc are exactly what the ISA says after that instruction. α reads them there. Flushed instructions never reach WriteBack, so a flush is — automatically — a stretch of stutters, and "flushed work has no architectural effect" lands in the invariant rather than in α. (For pipelines generally, constructing α is the famous hard part — Burch & Dill's flushing builds it by symbolically draining the pipe; Manolios's WEB refinement is the standard alternative when flushing fails. An in-order pipe with in-order retirement sits at the tractable end of that spectrum: draining is well-defined and short, with the bypass network priced in the invariant rather than in α.)

α's domain is a choice, and the statement above made it. The lean formulation leaves α partial — defined at retirement boundaries only, with mid-flight states described by I plus "within m cycles of the last retirement" and no architectural readout of their own; this is the form a retirement interface matches (RVFI's discipline), and the one to author. The statement's total α : I → States(ISA) is its completion along the run — α of a mid-flight state is α of its last retirement — well-defined as a function only when nothing architectural is destroyed mid-instruction; on a machine where that fails, the completion exists only as a simulation relation R ⊆ States(⟦RTL⟧) × States(ISA), and the per-cycle cell reads R-preservation instead of α-equality. The two forms prove the same refinement; which is available for this pipe (in-order retirement, writes only at WriteBack) is settled when α is actually written — the first experiment below.

The trace port is the designer-declared anchor. The core exposes retirement events (valid, instruction word, pc, exception status) on its own instruction-trace port — the interface the ecosystem's co-simulation flows check against a golden model. α should be defined to agree with the trace port's semantics: it inherits intent instead of guessing, and it makes trace-based co-simulation runs directly comparable evidence.

The measure is a retirement-gap bound

m bounds cycles-to-next-retirement, and every source of stutter is enumerable and individually bounded:

Two of those rows are now measured on a real execution (run-sim.sh, which runs the shipped core on a built image and records the retirement-gap distribution at the writeBack commit point). Over 200,000 cycles and ~50,000 retirements the observed gaps are: 3 cycles overwhelmingly — the taken-branch refill of the startup code's idle loop, i.e. the "pipeline refill" row at pipe depth — a small tail at 4–7 for the store sequence, and a handful of large gaps that are I-cache misses. And the cache row's f(B) is not just a shape but a law: sweeping the memory's wait states gives a worst gap that is exactly affine, gap_max = 24 + 8·B, whose slope is the 8-word cache line measured independently in the configuration record — each word of the burst refill pays the bus latency once. The measure's shape and the cache geometry corroborate each other from different directions. (Measured bounds are lower bounds on the true worst case: this is one execution, not a proof. What they establish is that the table's form is right.)

The last two rows are why the bus contract must carry a latency bound: with an unbounded response channel the measure does not exist and the refinement silently weakens from "instructions retire" to "instructions retire if the bus answers." State it conditionally: m exists given the contract's bound B; the SoC proof (L5/B2) discharges B for the actual fabric, with the off-chip serial-link path as the worst case.

Read quantitatively, the table is a worst-case execution time story with one honest complication and one honest mercy. The complication: fetch timing is history-dependent through the cache, so per-instruction bounds do not add exactly. The mercy: the cache is two lines, so the pessimistic miss-every-line bound is nearly tight, and a sound program-level bound is Σ w(i) with w charged at miss-inclusive rates — still literal addition, just of slightly larger constants; the interlock stalls depend only on the adjacent instruction pair, so they compose pairwise. Program-level bounds carry the same three side conditions as any WCET claim: B(config), trap-freedom along the path, and interrupts — handled by masking (mie, exact, the right mode for critical sections) or by response-time analysis on top. The load-bearing consumer is L5/04's graceful death: t_holdup ≥ t_epilogue^max prices a physical capacitor off the worst-case cycles of the quiesce path (IRQs masked) times a clock-period upper bound taken over the decaying-rail trajectory — the oscillator slows as the supply sags, so the seconds-per-cycle factor uses the slowest clock the epilogue traverses.

Traps and interrupts enter the statement, not just the proof

The commit case is a disjunction over the spec's step kinds: an ordinary retirement, or a trap/interrupt step of the machine-mode spec (L4) — mepc/mcause/mstatus updated and control redirected to mtvec, atomically. Preemption points are retirement boundaries: an instruction in flight is either retired or flushed, never half-committed — itself an invariant clause (07). Interrupt arrival is environmental; the measure's decrease is unconditional because a pending interrupt forces a trap step, not a stall.

What is deliberately not in the statement

No timing (L1 discharged it), no probabilistic terms (conditioning happened at the overview's †-lines), no bus implementation (contract-abstracted), no netlist (L2 licensed the RTL view). The statement is purely a relation between two transition systems — which is the payoff of the entire tower below it.

Obligations

1. Write α against the trace-port definition; check it on simulation traces before any proof (cheap oracle).
2. Settle α-total vs. R-relational for this pipe by writing the completion.
3. The stutter-source table's bounds, extracted from the emitted RTL (with 05's stage-graph extraction), and the conditional-on-B formulation with B named as an L5 deliverable.
4. The miss-inclusive w(i) table, validated against simulation; exported for L5/04's epilogue sizing.

Effort

Weeks to state precisely; stating it first is the layer's own first experiment, since every downstream choice (invariant clauses, IC3 targets) types against it.

L3/09 — The invariant

Background

The simulation cell of 08 is stated "from any state satisfying I" — and that qualifier is not a convenience, it is load-bearing. From a truly arbitrary state the cell is false: a state where the Execute stage's payload says "branch" while its control bits say "store" will step to something no ISA transition explains. Such states can never actually arise — but "can never arise" is a claim about all reachable states, and the reachable set of a machine with thousands of flip-flops is beyond any computation. The escape is one of the oldest ideas in program verification, due in essence to Floyd and Hoare: don't compute the reachable set — describe a superset of it that maintains itself. An inductive invariant is a predicate I such that (a) all initial states satisfy it, and (b) any single step from a state satisfying it lands in a state satisfying it. Induction then gives reachable ⊆ I for free, and the simulation cell only ever needs to be proved from I-states.

The catch — and the reason this chapter is flagged as the irreducible heart of the project — is that I must be invented, and the invention is forced to encode genuine understanding of the design. The property you want is almost never inductive by itself: "the retired state matches the ISA" says nothing about a half-finished shift or a mid-refill cache line, so a step from such a state cannot be shown to preserve it. To close the induction you must strengthen the invariant — add clauses describing every piece of in-flight machinery precisely enough that each clause's preservation follows from the others. Every stage register the generator emitted, every interlock corner, every implicit assumption in the RTL must be named in a clause. That is why proof effort tracks what this book calls invariant entropy — the number of independent design decisions I must describe — rather than gate count or spec size.

Invention is not entirely unaided, though, and calibrating the aid is this chapter's practical plan. Model checkers are tools that try to prove properties of finite-state systems automatically; the classical kind explores states exhaustively (dead on arrival here), but the modern kind — IC3 is the standard algorithm name — works by guessing and repairing invariant clauses: it accumulates small clauses, checks inductiveness with a SAT solver, and refines on failures. On the shallow, structural parts of an invariant (pipeline control sanity, handshake discipline) such engines routinely succeed unaided; on clauses expressing what a stage payload means, they mostly fail — that content is semantic, and no amount of clause search recovers it. The economics are favourable either way, because an inductive invariant is a certificate: whatever untrusted engine produced it, checking it means checking three entailments, each a SAT query with a machine-checkable proof. Let the engines mine the tedium, pay trust only at the checker, and measure where the boundary actually falls — that measurement, not any estimate, determines this layer's true cost.

Statement

Invent I — the irreducible content of the whole project, the one artifact no tool, decision procedure, or amount of compute produces. Everything else in the stack is either mechanical, certified, or measured; this is the part that is thought.

Invariant entropy, the governing quantity

Proof work is proportional to neither spec size nor gate count but to invariant entropy — the number of independent design decisions I must name. The operational test: a decision is free if the proof is generic over it or its consequence is recoverable by running the machine; expensive if I must describe it. Free here: datapath width, adder topology, decoder encoding. Expensive, and present: the pipeline's occupancy discipline, the interlock rule, the flush protocol, the two cache lines. Expensive and absent — forwarding networks, speculative state, miss queues, TLBs (05's table) — is what keeps the total moderate: the machine's entropy concentrates in one in-order pipe with the simplest possible hazard rule.

The clause sketch

What I must actually say, per the anatomy:

1. Pipeline control sanity: the stage valid/stall/flush arbitration bits are mutually coherent (no stage simultaneously firing and flushed; stalls propagate upstream contiguously).
2. Per-stage payload coherence: each stage's control bundle equals the decode of the instruction it travels with — the generated decoder's output, replayed. Wide, shallow, per stage.
3. In-flight semantics, per station: the iterative mul/div unit's accumulator holds the partial result with its counter consistent; a mid-flight memory transaction's address/data registers hold what the retiring instruction requires; an open LR reservation is consistent with the reserving instruction; the fetch front end's pc chain is consistent with the committed pc plus in-flight redirects.
4. Bypass/interlock correctness: every value routed sideways through the bypass network equals the value its producer will write back; where bypassing cannot serve (load-use, mul/div in flight, CSR effects), no reader advances past the unresolved writer.
5. Flush correctness: instructions younger than a taken redirect never reach WriteBack; the redirect target is the one the retiring step computed.
6. I-cache agreement: every valid line equals backing memory at its tag — modulo the fence.i window, whose obligation is exactly that software cannot observe the staleness.
7. TileLink transaction coherence: channel legality, source-ID bookkeeping, refill-burst accounting on the fetch side (06).
8. CSR coherence: mstatus.MIE/mie/mip consistent with the spec state; the PMP configuration consistent with the checks the access paths apply (07).
9. α-well-definedness: at retirement boundaries, the architectural readout is total.

Clauses 1, 4, and 7 are exactly the local control invariants IC3-class engines find unaided; 2 is wide but mechanical; 3, 5, 6 carry the semantic content the human supplies; the glue — that the clauses jointly imply the retirement step matches the ISA — is human work.

The automation calibration

An inductive invariant is a certificate: init ⊆ I, I ∧ T ⊆ I', I ⊆ P — three queries, each LRAT-checkable. So untrusted engines may invent clauses and we pay only for checking. The plan: build the invariant-checking path first, throw IC3 at clauses 1/4/7 phrased as safety properties, and measure the hit rate before hand-authoring anything. Expect the engines to clear the structural majority and die on clauses 3/5/6 — but measure, because the split determines the layer's real cost.

The state space forbids the alternative outright: reachability and model checking over the full machine are dead on arrival; refinement plus induction is the only game (L2/02 said the same from below).

Structure of the work

The pipe seams the authoring naturally: clause families attach to stages and to plugins (05's tour is the index), so the invariant parallelises across stations in a way a monolithic state machine would not. The per-instruction quantification lives in 10; this file owns the machine-wide skeleton those obligations plug into.

Obligations

1. Phrase the clause sketch as machine-checkable predicates over ⟦RTL⟧'s state.
2. The IC3 calibration run; record the found/failed split.
3. The glue lemma: I + retirement transition ⟹ the ISA step (with 08).

Interface (up). This invariant is the S-refine seam (iface_L3, rtlBeh = archBeh): the arrow from RTL to ISA. L3/08's cosim oracle — 1631 instructions matched against spike — is its executed precursor, and the gap between that oracle and the theorem is exactly the invariant α developed here.

Effort

The heart of the layer's estimate — yet the volume is small: the genuinely irreducible content is plausibly a few hundred lines of clauses plus the glue lemma. The years are the surrounding machinery (symbolic simulation, bitvector automation, the stuttering framework), not the thinking.

L3/10 — The per-instruction obligations

Background

With the invariant (09) holding the machine's global coherence, what remains is to check each instruction individually: that the hardware's handling of add matches the spec's add, the hardware's beq matches the spec's beq, and so on through the instruction set. The technique that discharges each one is symbolic execution: instead of running the hardware on particular values, run it on variables. Start from an invariant state with the instruction at a known station and symbols in the registers, walk the machine to the instruction's retirement, and the final state comes out as a formula — "register rd now holds x + y, the committed pc advanced by 4." The obligation is then that this formula equals what the Sail clause computes, which is a question about fixed-width integers (bitvectors) that SMT solvers — SAT solvers extended with built-in theories of arithmetic — answer mechanically. One symbolic run covers all 2⁶⁴ concrete operand pairs at once; that is the entire trick.

The reason this chapter can promise "a lot of lemmas, almost no thinking" is a structural dividend from the invariant: the bypass/interlock clauses cut every dependency between instructions at the operand read. Whatever ran previously, an instruction's sources equal the committed (or correctly-forwarded) values — so each per-instruction lemma starts from the same characterised conditions, independent of its neighbours, and the set of lemmas is embarrassingly parallel. The cost structure follows: build the symbolic-execution harness once (the real expense), then each additional instruction is a template instantiation. Per-case thought reappears only where an instruction contains an internal loop — the iterative multiplier/divider — in the form of a small loop invariant, the classic Floyd–Hoare pattern in miniature.

Statement

The wide-shallow quantification: for each instruction of the configuration record, the retirement case of 08's cell — from an invariant state with this instruction in flight, the retiring effect equals the Sail step. High spec entropy, near-zero invariant entropy: a lot of lemmas, almost no thinking, and most of it plausibly automatable per instruction.

The obligation classes

Decode — the bridge between L4's Sail decoder and the generated decoder of the emitted core (with the RVC expander composed in front: a 16-bit word's obligation goes through the expansion function first, checked against the standard's own table):

∀ word w:  the control bundle produced for w  =  image of Sail-decode(w)
           (exhaustive: every word decodes or raises the illegal trap;
            exclusive: one instruction class per word)

Per-encoding, SAT-shaped, across both instruction widths, plus the trap sweep: every word the decoder rejects must reach the illegal-instruction trap step (F/D, the S-mode space, and the reserved regions minus the UB set), and absent-CSR reads trap at execute. The words in L4/03's spec-UB set — reserved encodings the decoder accepts — generate no obligation at all: the spec's havoc step is refined by anything, which is precisely why the UB clause exists.

ALU and comparisons — word-level lemmas per operator: the Execute-stage result equals the Sail arithmetic — bitvector identities, discharged by SMT; the netlist structure of the adder was L2/05's business and never appears here. Branches: the comparison drives the redirect exactly as Sail's branch semantics, with the flush obligation carried by the invariant's clause 5.

Multiply/divide — the place 09's clause 3 has real content: the iterative unit's loop needs the invariant acc = partial(x, y, counter) with the measure ticking; the lemma composes the loop to the Sail mul/div/rem semantics, division-by-zero and overflow cases included (the standard fixes both — no traps, defined results).

Loads/stores/atomics — address generation, byte-lane select and sign/zero extension vs. the Sail memory access, alignment traps per the spec's choice, the PMP check on every access, and the bus's role contract-abstracted — the lemma says "the value the contract returns for this address," never what RAM did. The A extension adds the AMO read-modify-write lemmas (the atomic ALU's operation table vs. Sail's) and the LR/SC pair against the recorded reservation choice (L4/02).

CSR instructions — csrrw/csrrs/csrrc and immediates against each implemented CSR's semantics: the machine-mode registers, PMP, and counters from the Sail import, and the custom control CSRs against the residual authored spec (L4/01). Reads of the absent CSRs belong to the trap sweep.

Fences — fence is a no-op on this single-hart, in-order machine (a lemma, not an assumption — and it must survive the device-memory ordering question at the TileLink port); fence.i invalidates the I-cache and refetches — the obligation pairs with the invariant's cache-agreement clause.

Why this class is cheap per element

Each lemma is: symbolic execution of one instruction's pipeline transit from an I-state, compared against one Sail clause — bounded, automatable, independent of every other lemma, with the interlocks supplying the independence. The cost is proportional to the number of instructions, not to any interaction between them.

Obligations

1. The decode equivalence + the unimplemented sweep (gated on the configuration record and L4's Sail import).
2. Per-class lemma templates: one worked instance each (an ALU op, a shift, a load, a CSR op), then mechanise the remainder.
3. The fence.i lemma, jointly with the invariant's cache clause.

Effort

Months, dominated by building the symbolic-execution harness once; per-instruction marginal cost should approach mechanical. If it does not, something is wrong with the harness, not the instructions.

L3/11 — The bus and debug obligations

Edge: this file is the theorem the node carries — the request-discipline guarantees the core proves, entering 09's invariant as clauses, the interface half of the L3→L4 refinement edge. The ports and debug module as structure are the node, 06.

The core's half of the port bargains, as the clauses it guarantees. What the ports are — the instruction and data masters, the debug side door, and what their absences buy — is the node, 06; here are the promises those masters prove.

The instruction-port guarantees

The I-cache's refill master. Guarantees, provable as invariant clauses (09 clause 7):

Gi1  refills are well-formed: line-aligned base, legal size, a single
     source ID per outstanding refill, beats accepted per the handshake
Gi2  a refill, once started, is not abandoned (except by reset)
Gi3  fetch addresses are execute-region addresses (no device-region fetches)

The data-port guarantees

The data-side master:

Gd1  requests are legal TileLink: aligned to their size, permitted opcodes,
     source IDs within the negotiated set, stable until accepted
Gd2  byte masks well-formed and consistent with the retiring access width
Gd3  no speculative writes: a store's request issues only for a retiring store
Gd4  atomic requests carry the correct AMO opcode and operand; an SC issues
     only against its own valid reservation

Gd3 is where the pipeline meets the memory: flushed instructions must not have touched the bus.

The debug non-interference lemma

The hardware-side obligation for the debug module is only that inactive means invisible — a non-interference lemma of the same shape as 07's masked-interrupt one. It discharges the debug-inactive hypothesis (no halt request in flight, no abstract command executing) that the node (06) threads once through 08's statement.

Obligations

1. Gi1–Gi3 and Gd1–Gd4 as invariant clauses, with the simulation oracle re-run against this core first (execute a real image with the clauses asserted continuously; a clause that survives a real run is worth stating, and one that does not is found here rather than in a proof attempt).
2. The debug non-interference lemma, and the debug-inactive hypothesis threaded through the statement.
3. The burst-length/line-size agreement between the cache and the refill master (one constant, two readers — pin it in the configuration record).

Effort

Weeks; the protocol clauses are IC3-shaped. The value is in the statement discipline — every later surprise about "what does the bus promise" lands here or in L5, never diffusely.

L3/12 — The trap and interrupt obligations

Edge: this file is the theorem the node carries — the proof that the trap/interrupt machinery refines the machine-mode ISA, part of the L3→L4 refinement edge. The trap/interrupt mechanism as an object is the node, 07.

Statement

Prove the trap and interrupt machinery refines the machine-mode spec: the imported Sail subset for everything standard. The mechanism itself — the CSRs, the CLINT/PLIC wiring, the synchronous surface — is the node, 07. The proof obligations:

1. Trap-entry atomicity: mepc/mcause/mstatus update and the redirect to mtvec happen as one spec step — no observable intermediate, no partially-retired instruction underneath (08's disjunction stays clean).
2. mret unstacks and redirects exactly per the spec.
3. Preemption only at retirement boundaries: an instruction in flight is either retired or flushed, never half-committed — an invariant clause (09), and the reason the simulation cell needs no third case.
4. Delivery gating: a trap step is taken exactly when mstatus.MIE ∧ (mip ∧ mie) ≠ 0 at a boundary (or a synchronous exception retires); no lost interrupts — the persistence of a source lives in the CLINT and the PLIC's gateway/pending machinery (a device-model property plus software's claim/complete discipline), hence a Sys(F)-level claim, split explicitly.
5. Precise exceptions on the memory path: a faulting access (denied response, misaligned, PMP-refused) traps with the correct cause and no side effect — the lemma family where the memory system meets the trap machinery.
6. Non-interference: with mstatus.MIE clear and no traps raised, behaviour is exactly the trap-free machine — the lemma that lets every other L3 file ignore this one, quarantining the risk.

Anchors against spec-side error

The imported half is anchored by the standard's own artifacts: the riscv-arch-test suite run against the imported model, and RVFI-style retirement checking for what "an interrupt retired correctly" observably means. The device half (CLINT/CLINT-compare semantics, PLIC claim/complete) is anchored by the de-facto and ratified documents those devices implement, formalised first and then diffed against the generated RTL. The working-software corpus — the ecosystem's own interrupt-handling code and test suites — is what the composed spec must make correct; extracting the interrupt-facing paths and running them against the draft spec is the standing check.

Obligations

1. The six proof obligations above, non-interference (6) first.
2. The delivery split stated precisely: core-side gating proved here, source-side persistence delegated to L5/03's CLINT/PLIC models by name.
3. The software corpus: extract interrupt-facing code paths from the ecosystem's test programs; run each against the draft spec.

Effort

Months, but mostly standard months: the imported half rides the Sail model and existing compliance machinery, and the interrupt sources are standard devices with documents. The open-ended risk — spec fidelity for the small authored residue — is priced in the ledger as S3.

L2 — Netlist ↔ RTL equivalence

Node — the synchronous machine: flops plus combinational logic over a Boolean vector, Mealy(N) (00), well-defined only under the standing well-formedness hypothesis that survives the digital crossing (01). Edge up — the CEC (a horizontal equivalence, not an abstraction step): Mealy(N) ≈ρ ⟦RTL⟧ — the netlist machine equals the RTL machine under a register correspondence ρ, via licensed deletions (02), ρ (03), the equivalence certificates (04), and the hard cones (05). Note the proof-order inversion: this edge consumes L3's object ⟦RTL⟧, so it is proved after L3 despite sitting below it in the tower — numbering is artifact altitude, not logical dependency. (The book's top-down reading order happens to agree: L3's chapters precede these.)

Background

Synthesis compiled the emitted RTL into the netlist the flow hardens: 51,359 standard-cell instances (drawn from 96 cell types) with mangled names and aggressively restructured logic, growing further in place-and-route as clock trees, hold buffers, and physical cells are inserted. This layer proves the compilation preserved meaning — not by trusting the tool, but by checking certificates the tool's run can be made to emit. The route: define the netlist's semantics (00), check it is electrically sane (01), delete the instances that compute nothing under explicitly licensed theorems (02), extract the register correspondence from the flow's own run (03), and prove per-register-boundary equivalence by certificate, with exploratory SAT confined to where no certificate exists (04, 05).

Statement

There is a register correspondence ρ — a bijection between RTL state elements and netlist flops, up to opt_dff-eliminated constants and resizer cloning (its existence is exactly F5) — such that, after the three licensed deletions,

Mealy(N) / (delete PHYSICAL · collapse clock to the global tick · collapse buffers)
    is bisimilar under ρ to   ⟦RTL⟧,   from matched reset states.

Established by certificates, with exploratory SAT confined to where no certificate exists. The N here is the shared object of the overview's tower: one parse of ChipTop.mapped.v (and its post-P&R successor) serves L1's LVS target, L1's STA subject, and this theorem's left-hand side.

Subcomponents

Interfaces

Consumes: the hardened netlist, RTL, ⟦·⟧ (L3), the synthesis flow, per-cell Boolean functions (L0). Exports: to L1, N with identified registers/clock/reset; to L3, the licence to reason about ⟦RTL⟧ instead of the netlist.

Axioms introduced

None surviving. S1 (netlist semantics) is derived — per-cell Boolean shadows (L1/06) + the bridge theorem (M5) + LVS (L1) yield it as a conclusion (00) — and X1 (parser fidelity) is an ordinary verified-parser obligation; both are in Axioms' Discharged table. F5 (does ρ exist?) is the layer's load-bearing unknown, decidable by 03's experiment.

The layer's shape

Everything reduces to the register boundary. Only ports and state elements need correspondence — internal restructuring is exactly what CEC absorbs — so the RTL-to-netlist gap is the question "do the flops correspond?" (F5), and every other file supports answering or exploiting it: 00–01 make the two sides comparable objects, 02 shrinks the problem 13×, 04 checks the cones between corresponded registers, 05 handles the cones where checking needs a different calculus. The methodological corollary: never reconstruct word structure from bits — words live on the RTL side of ρ; and never compare against an independently-written model — structural similarity is what makes any of this tractable.

The proof, structured

Take one tiny sequential circuit — a flop q whose next value is ¬((a·b)+c) — and follow that object down through the layers: a behavioural expression, then a cell netlist, then transistors.

Definitions.

• R, I, O — the RTL register bits, input bits, output bits.
• ⟦RTL⟧ (from L3) — a Mealy machine on states 𝔹^R: a next-state function δ_r : 𝔹^R × 𝔹^I → 𝔹 for each r ∈ R, and output functions λ_o.
• N — the hardened netlist; F its flip-flops. Each cell instance denotes a Boolean function, its Liberty entry.
• N_f : 𝔹^F × 𝔹^I → 𝔹 — the function of flop f’s combinational fan-in cone (cell functions composed along the nets). These define Mealy(N).
• ρ : R → F — a bijection; ρ(r) is the flop holding bit r. For a netlist state s ∈ 𝔹^F, s∘ρ ∈ 𝔹^R is the RTL state read off the flops.
• s0, …, s7 — the intermediate networks at the boundaries of the synthesis (ABC) script, the eight snapshots cec/trail-cec.sh records. Flops are mapped (dfflibmap) before ABC, so every s_k is a combinational network over the same flop boundary F — this is the no-retiming fact. s0 = the front-end output (proc/flatten/memory/opt/techmap); then s1 after fx, s2 after mfs, s3 after strash, s4 after the rewrite/refactor/balance block, s5 after the fraig sweep, s6 after amap, s7 after &dch/&nf. Each s_k thus defines a cone function per flop; s_k ≡ s_{k+1} means these agree for every flop.

Goal. for every r ∈ R (write f = ρ(r)) and all (s, i) ∈ 𝔹^F × 𝔹^I: N_f(s, i) = δ_r(s∘ρ, i) (and N_o = λ_o under ρ, for outputs). A combinational identity — the one-step ρ-commutation; the lift to trace equivalence is L3’s (foot of proof).

Each leaf (▸) is a tool run whose output is a certificate we can independently check, or a checker we assert correct. Status: ● holds · ◐ partial · ○ open.

Proof.

• 1. Mealy(N) is well-defined — each N_f is total. ◐
  • 1.1 · 00 each cell denotes its Liberty function (this fixes the cone composition; call it S1). ▸ celltopo derives each library master’s function from its transistor switch-network and asserts equality to Liberty; the derivation is the certificate (the conducting-path formula), independently checkable. ● 311/437 masters · ○ flops, tristate.
  • 1.2 · 01 N’s combinational graph is acyclic and single-driven (W1–W4), so composing 1.1 along the nets terminates in a total N_f. ▸ the W1–W4 checker — finite structural checks on N; checker asserted correct. ◐
• 2. ρ is a bijection R → F (F5). ▸ 03 the flop→name table read from the Q-nets; certificate checkable as injective and onto R. ● 10,873/10,915. Figure: DFF ≙ register q.
• 3. N ≡ N′ cone-wise, where N′ drops the physical / clock / buffer cells. ▸ 02 per class: physical cells drive no logic net; buffer/clock cells have function = identity (by 1.1) — one checkable certificate each. ◐
• 4. N′_f(s, i) = δ_r(s∘ρ, i) — via the pass trail. Figure: the AOI21 cone computes ¬((a·b)+c).
  • 4.1 adjacent snapshots are cone-equal, s_k ≡ s_{k+1}. ▸ 04 their miter as CNF, UNSAT by minisat (modules) / ABC cec (die); exact passes one miter each, mfs 6,172. The CNF is the certificate; correctness = an independent solver’s UNSAT (miter polarity falsification-tested). ● s0 … s7.
  • 4.2 hence s0 ≡ s7 (4.1, transitivity); and s7 ≡ N′, since the trailing buffer/upsize/dnsize are function-preserving and the P&R inserts are exactly step 3’s deletions. ●
  • 4.3 s0’s cones equal δ (the front end RTL → s0: proc / techmap / opt). ▸ no certificate yet. ○
  • ⇒ 4.2 gives N′_f = (s0-cone); with 4.3, = δ_r. Conditional on 4.3.
  • 05 arithmetic cones (mul / div) take the same 4.1 equalities via width-generic template theorems, where SAT starves. ◐
• 5. Goal. N_f = (by 3) N′_f = (by 4) δ_r(·∘ρ); well-defined by (1), quantified over all of R by the bijection (2). ∎ Sound modulo the open leaves 4.3 (front end) and the 1.1 master-coverage gap.

Lift (L3, not here). With the reset-bit certificate reset_f = reset_r (03, ○; the IBuf unreset residual is its failure mode), the Goal lifts to Mealy(N) ≈ρ ⟦RTL⟧ by one cycle-induction step in L3 — trivial because ρ shares the state.

Open problems

1. F5 — run 03's reproduction; both outcomes are results.
2. The ABC trail patch and checker (04) — the cheapest site anywhere in the project for the congruence-certificate architecture.
3. The mul/div parameter check (05) — confirms the multiplier stays iterative, keeping the hard problem class away.

First experiments

Instrument the synthesis (03) — the flow is ours to re-run, so ρ is logged, not excavated. Alongside: promote W1–W4 to lemmas (01), and state the SRAM macro contracts (02).

Effort

6–9 months; the most likely place for an early concrete result after L1's SDC work. Cost scales with the certificate trail length, not the design size.

Reading

Kuehlmann/Brand lineage on SAT sweeping; ABC's rewrite/refactor/resub. Kaufmann & Biere on PAC certificates for multipliers. CompCert for the verified-pass vs validated-pass calculus — they validated register allocation for exactly the reasons 04 validates the rewrite trail.

L2/00 — The netlist object and its Mealy semantics

Background

Between the RTL a human wrote and the geometry the fab printed sits the netlist: the design expressed as a list of gates and the wires connecting them. It is produced from the RTL by synthesis — a compiler, in every meaningful sense: it parses the Verilog, maps the described logic onto a fixed vocabulary of available gates, and optimises hard along the way, restructuring the logic beyond recognition while (one hopes) preserving its function. The gate vocabulary is the standard cell library: a catalog of a few hundred pre-designed, pre-characterised primitive circuits — NAND gates, inverters, flip-flops, multiplexers, each in several drive strengths — provided with the fabrication process. Everything computational on the die is an instance of one of these cells; this design's synthesis netlist has 51,359 of them, drawn from just 96 cell types, and place-and-route adds more (clock buffers, hold-fix buffers, physical cells) before the netlist is final.

The netlist's file format is structural Verilog — the same language as the RTL, but stripped of everything programmatic: no always blocks, no assignments, no control flow, just instance declarations ("here is a NAND2 named _04531_, its pin A connects to net _1234_...") repeated a few hundred thousand times. Where the RTL is a program, the netlist is a parts list with a wiring diagram, and its semantics is correspondingly simpler to define — which is why this chapter is the cleanest formal artifact in the book.

That semantics is a Mealy machine: the classical mathematical form of a clocked circuit, consisting of a state (here, one bit per flop — flip-flop, the library's storage cell), a next-state function, and an output function. Reading a Mealy machine off a netlist works because the netlist separates cleanly into its sequential cells (the flops — which cells those are is declared in the library, a lookup rather than an inference) and everything else, the combinational cells, which form a DAG — a directed graph with no cycles — from flop outputs and input ports to flop inputs and output ports. One clock cycle means: evaluate the DAG in dependency order, each cell applying its little Boolean function; then update every flop simultaneously with the value at its data pin. The preconditions that make this well-defined (no cycles, exactly one driver per wire, nothing floating) are precisely the well-formedness checks of 01.

Statement

Define N and Mealy(N) — the shared object of the overview's spec tower and the left-hand side of this layer's theorem.

One parse, three consumers

N = ⟦ChipTop.mapped.v⟧ (and, for the physical layers, its post-P&R successor) under a single parser. The same object is: L1's LVS target (N_intended), L1's STA subject, and this layer's left-hand side. That identification is used silently everywhere and must be established once — it is X1's obligation, a verified parser for a deliberately tiny language.

Structural Verilog is a file format, not a programming language: module instantiations, wire declarations, port connections — ~20 productions, no always, no assignments, no scheduling, no delta cycles, no X literals. The admissible-subset move from L1/00 (GDS) applies again: parse exactly what production output uses, reject the rest.

The semantics, in outline

State  = Flop → 𝔹                        (5,774 bits at this hierarchy level)
Input  = Port_in → 𝔹
δ, λ   = topological evaluation of the combinational DAG through
         each cell's Boolean function (L1/06's (A)), then flop update

~30 lines of definition. Its preconditions are exactly 01's checks: acyclicity (W3) makes the topological evaluation well-defined; one-driver-per-net (W1) makes net values functions; no floating reads (W2) closes the evaluation; inertness (W4) lets the physical cells drop out of State entirely.

Registers are lookup, not inference. The library declares which cells are sequential and which pin is clock/data/reset/enable — identifying State is a table join, not pattern recognition. Clock and reset network identification is mechanical reachability (L1/10's cleanliness check).

What this semantics is, epistemically

Two facts that took the project a while to get right:

S1 is derived, not posited. "The netlist's Mealy semantics is the right semantics" was originally an axiom; it is now the conclusion of the physical stack — per-cell Boolean shadows (L1/06) + the bridge theorem (M5) + LVS (L1) yield it. This layer consumes that conclusion; nothing here assumes it.

The two-valued semantics is the tracked fragment. Mealy(N) over {0,1} describes the machine only inside the bridge theorem's hypotheses; the honest ambient object is the ternary machine over {0,1,X} (L1/03's value lattice), and the two-valued view is entered by X-elimination at reset and maintained by timing closure. Where the RTL deliberately leaves state uninitialised, implementation-X refines the spec's own reset nondeterminism rather than being eliminated — the bisimulation of 03 is stated from reset-reachable states for exactly this reason.

Bits, not words. Mealy(N) is over individual nets; the word structure lives only on the RTL side, and 03 explains why it must never be reconstructed from below.

Obligations

1. X1: the verified parser — CompCert-style validated front-end for a 20-production grammar. Standard work, no empirical content.
2. The ~30-line semantics, written once, with its four preconditions imported from 01 as hypotheses rather than assumptions.
3. The pin-direction table (43 names, declared not inferred — tools/netgraph.py's table is the prototype) promoted into the semantics as the library signature.

Interface (below). This object is where the physical chain hands off to the functional chain. The S-extract seam is the theorem that the extracted layout — celltopo-grounded cells (L0), routecheck connectivity (L1), LVS device-match — actually is this theNetlist. It composes three certificates that each pass on the scoreboard but that no obligation here joins into one behaviour equality; that composition, not any single check, is the open work.

Effort

Weeks. This is the cleanest formal artifact in the entire stack — the reason the bottom-up route was attractive before L3's census tax was measured — and it should be built early since every other file in L2 types against it.

L2/01 — Well-formedness: checked, not assumed

Background

The Mealy semantics of 00 presumes the netlist is electrically sane, and each sanity condition has a concrete physical failure behind it. A net (wire) is driven by the gate output connected to it; if two outputs drive one net and ever disagree, the result is contention — one transistor pulling the wire toward 1.8 V while another pulls it toward ground, a fight that produces an invalid intermediate voltage and, sustained, a damaging short-circuit current. A gate input attached to a net with no driver is floating: its voltage is set by nothing, drifts with whatever charge leaks nearby, and reads as an arbitrary, possibly time-varying bit. And a combinational cycle — a loop of gates with no flop breaking it — has no settled value to compute; physically it is a feedback loop that may oscillate forever. The checks W1 (one driver per net), W2 (no floating reads), and W3 (acyclicity) rule these out; W4 (inertness) verifies that the cells about to be deleted in 02 genuinely touch nothing logical.

Two pieces of circuit vocabulary appear in the results and deserve a sentence each. A tri-state driver is a gate output with an enable pin: enabled, it drives its value; disabled, it electrically disconnects (the "third state," high-impedance or Z). Tri-states are the legitimate way for several drivers to share one wire — legitimate exactly when the enables guarantee at most one driver is on at a time, which is the question W1 must settle for each shared net it finds. And a ring oscillator is a loop of an odd number of inverters — a deliberately built combinational cycle whose value can never settle, so it oscillates at a frequency set by the gates' delays. It is the standard way to generate a clock on-chip, it lives inside this design's PLL, and it is supposed to violate W1 and W3: it is the one part of the die whose job is to be unstable. The satisfying result below is that the violations found are exactly the ring oscillator and nothing else — the analog island is precisely where the structural checks say it is.

Statement

The four preconditions of 00's semantics, decidable on the hardened netlist by the layer's checker (to be re-run against this flow's output). The tool discipline carries over unchanged: every pin name classified explicitly, and the checker exits non-zero on an unknown pin rather than guessing a direction, since a misclassified output silently turns real contention into a clean bill of health.

W1 discharges structurally — and the discharge is idiom-dependent

The contended nets are einvp/einvn pairs with the same enable net on TE and TE_B — complementary polarity, so exactly one conducts, by construction. It is the oscillator's delay-trim multiplexer; no functional reasoning needed. The luck should be recognised as luck: a decoded tri-state bus ("at most one select high") would need a reachability proof over the decoder's state space — L5-difficulty work leaking into a well-formedness check. The general rule: tri-state sharing discharges structurally iff the enables are complementary by wiring; anything else escalates.

W3's expected verdict, and what a hit would mean

This design has no on-die oscillator, so the expected W3 verdict is zero cycles and zero contention outright — there is nothing that should violate the synchronous discipline. Any hit is therefore a finding, not an excision candidate: a cycle would be a generator or synthesis defect, and a multi-driver net a mapping bug. The check's value inverts from delimiting a known analog region to certifying there isn't one.

W2 is a hierarchy artifact with a real residue

Undriven-read reports localise to macro boundaries — nets fed by the SRAM macros' outputs, whose drivers are not standard cells in this file (the unused second-port outputs of the memory macros are the expected bulk). Reducing the raw report to genuine floats needs the macro interface list; expect ~0 residue. It must be discharged rather than waved at: a real floating read is a node with no restoring driver, hence permanently X — outside L1/06's invariant sets, not merely untracked.

W4 caught the tool

First run: 118 violations, all conb_1 — a constant generator (drives HI/LO) misfiled as inert filler. Correcting the classification gave 0 and brought the physical total to exactly 235,566, independently matching Findings' census. The inertness check catching a misclassification of its own configuration is the argument for having it: 02's 85.5% deletion rests entirely on this property.

What W1+W2 buy beyond the semantics

They are the licence to work three-valued rather than four-valued (L1/03): HDL logic's fourth value Z (undriven) is structurally excluded — every net has exactly one driver and every read is driven — so Z is deleted from the value lattice rather than modelled.

The within-cell half of the no-contention condition (PUN/PDN duality) is not checkable at this level — it needs transistor netlists; see L0/06.

Open problems

1. Reduce W2 against the macro interface list (an afternoon, given the LEF or module ports).
2. Promote the checks from tool runs to lemmas against 00's formal netlist — same computations, checked once inside the proof.

Effort

Done, at tool level. The promotion to proof-level lemmas is days once 00 exists.

L2/02 — The licensed deletions

Background

A newcomer's mental image of a chip — gates computing things — describes a modest fraction of one. The finished layout's instance census tells the real story: alongside the logic sit physical cells, present for electrical and manufacturing reasons — decaps (decoupling capacitors, smoothing the power supply against demand spikes), tap cells (connecting the transistors' silicon wells to the rails to prevent latch-up), fill cells (spacers keeping the fabricated layer densities uniform), and antenna diodes (protecting gates from charge build-up during fabrication) — usually outnumbering the logic outright once fill is inserted. Another large class is the clock tree: the clock signal cannot physically drive thousands of flops from one wire, so it is distributed through a tree of buffers — carefully balanced so every flop sees its edge at nearly the same moment, and including thousands of pure delay buffers inserted only to fix hold timing (this flow's hold repair alone inserts several thousand). Add ordinary signal buffers and inverter pairs, and the logic that L3's semantics actually describes is a minority of what gets fabricated.

For the equivalence proof, all of this must go — the RTL has no counterpart for a decap — but the book's discipline is that nothing is deleted by classification convention. "It's a fill cell, ignore it" is an assumption; "its pins touch only power rails, therefore it cannot affect any logic net" is a theorem, checkable per cell. Each deletion class below carries its licence: the physical cells go by the measured W4 property, the clock tree collapses into the sentence "all flops update together" — a licence that is exactly as good as L1's timing theorem, and conditional on it — and buffer chains collapse by library lemmas (buf is the identity; two inverters cancel).

One more object appears here: the macro. Not everything on the die is standard cells — larger pre-built blocks are placed as opaque units. In this design there are exactly five macro instances of three kinds, and all are the same thing: SRAM arrays (the two data-memory banks, the two instruction-cache data arrays, and the tag array). These are not deleted but become holes in the netlist, each closed by a contract: the macro's promised behaviour (a synchronous memory with the port discipline its datasheet states), assumed by this layer and discharged elsewhere. What makes these holes unusually honest is that the macros come from an open generator: their transistor-level netlists, layouts, and characterisation are all published, so the contract is checkable-by-effort — at transistor level, by L0's machinery — rather than a foundry black box that no analysis can enter. And the obligation is parametric: one proof per macro kind covers every instance and every depth the generator emits, which is why memory size costs area, never verification.

Statement

Reduce the hardened netlist to the instances that carry logical content, with each deletion licensed by one named obligation rather than by classification convention. The synthesis netlist starts at 51,359 cells (10,416 sequential); place-and-route adds the clock tree, hold buffers, and physical cells, and the exact census of the final layout is a measured deliverable of the flow (findings). The classes and their licences:

Two remarks on the big rows. The physical deletion is the largest single simplification in the project and rests entirely on W4's one property. The clock deletion is the bridge theorem's payoff made concrete: the entire tree — including every delay buffer that exists purely to shape the arrival function — vanishes into the sentence "all flops update together," conditional on L1's hypotheses; the deletion is exactly as sound as timing closure is. One genuinely new entry versus a flat design: this netlist's clock tree contains clock gates (the ICG cells L3/02 carved out as primitives), so the collapse must carry the gating condition — "all flops whose gate is enabled update together" — which is the gated-clock soundness obligation L1 owns.

The macro contracts

Per kind, the contract states: a synchronous memory of the given geometry — one read-write port (the second, read-only port of the generator's interface is tied off and its outputs unused, a fact W-checks must see rather than assume), byte write masks where present, one-cycle read latency, disabled-read data unconstrained (matching L3/03's X idiom). Three kinds, three contracts, five instances covered. The discharge routes, in increasing ambition: assume with the published characterisation as evidence (X4-class, the starting point); simulate the published transistor netlist against the contract (the generator's own regression, replayed); prove at L0's level from the published layout — open-collateral analogues of the standard-cell obligations, amortised exactly like them.

What remains

|State| = 2^10416 at the synthesis netlist alone. That number settles methodology once and for all: refinement plus induction with a supplied invariant; never reachability, never model checking. Every plan that begins "enumerate the reachable states" is dead on arrival, which is why L3's invariant is the project's irreducible content.

Obligations

1. State each deletion as a theorem over 00's semantics: Mealy(N) ≃ Mealy(N ∖ PHYSICAL) given W4; the clock collapse given L1 (with the gating condition); buffer collapse given the library lemmas.
2. The three macro contracts, stated; the tied-off second ports verified structurally; the discharge route per kind decided and recorded in the ledger.
3. The BUF/INV collapse must respect 03's ρ — inverter absorption flips polarity, and the register mapping must record per-bit polarity or the CEC will chase phantom mismatches.
4. The final-layout census, measured and pinned when the flow closes.

Effort

Weeks for the deletion theorems; the macro contracts are days to state, with their deeper discharge routes priced as optional depth.

L2/03 — The register correspondence ρ (F5)

Background

To compare the netlist against the RTL at all, you must first say which netlist flop corresponds to which RTL register bit — and synthesis has done its best to obscure the answer. The RTL declares reg [31:0] reg_op1; the netlist contains flops named _04531_, _04532_, … with every trace of the word structure flattened away, the names mangled into meaningless serial numbers, and the optimiser having possibly removed some flops entirely (one whose input is provably constant needs no storage), duplicated others (a heavily-loaded flop cloned so each copy drives half the fanout), or absorbed a nearby inverter so the flop stores the logical negation of its RTL bit. The mapping that survives all this — RTL bit to netlist flop, up to those enumerated deviations — is called ρ here, and whether it exists in clean form is this layer's central empirical question.

Why does the whole equivalence effort hang on the registers specifically? Because state elements are where a sequential comparison can be cut. If every RTL register bit is matched to a netlist flop, then proving the two designs equivalent for all time reduces to proving, once, that between corresponding register boundaries the two compute the same combinational function — a finite, per-cone check (04). Without the matching, the comparison is between two arbitrary state machines whose states don't align, which is a vastly harder problem (equivalence would need its own invariant, L5-style). Commercial equivalence-checking flows depend on this so completely that commercial synthesis tools emit a hint file recording exactly what they did to every register; the open-source flow emits nothing, which is why ρ must be recovered.

The recovery strategy here is structural, not archaeological: the build is ours. The netlist of record is produced by a flow this repository runs, from pinned sources, and synthesis is essentially deterministic — so ρ need not be reverse-engineered from an artifact at all: re-run the flow with instrumentation, log every register-affecting optimisation as it happens, and the mapping falls out as a byproduct of the run. This is the reproducible-build discipline that software supply-chain security relies on, pointed at a proof obligation — with the advantage over any inherited artifact that there is no provenance gap even in principle: the netlist and its witness are two outputs of one run.

Statement

Exhibit ρ: a mapping between RTL state elements and netlist flops — a bijection up to opt_dff-eliminated constants and resizer cloning (1→many) — such that 04's bisimulation can be cut at register boundaries. Whether ρ exists is F5, the layer's single load-bearing unknown, and it is decidable by experiment rather than by argument.

Resolved: ρ is readable straight off the netlist (F5)

The experiment was run, and it did not need the instrumentation the plan below anticipated. The premise "synthesis mangles the names into meaningless serial numbers" is true of the flop instance names (_04531_) but false of what carries the register's identity: the flop's Q-net. yosys anonymises the instance but names the net the flop drives after the RTL hierarchical signal — \system.tile_prci_domain.…frontend.icache.refillError, \buf_pc[3], and so on. Measured on the netlist of record, 10,873 of 10,915 flops (99.6 %) carry the RTL register name on their Q-net. So ρ is not archaeology and not a tool patch: it is a hypothesis readable from the shipped artifact, and the 42-flop residue (plus any constant-folded or merged register) is exactly the enumerated-deviation set, settled by the equivalence check that consumes ρ.

And it is not merely readable but usable: 04's equivalence run matched RTL to netlist by name alone, with no hint file, and the matcher paired cones only where a name on each side corresponds — which is ρ recovered and consumed in one step. This was confirmed at two scales: on a carved-out cone (IBuf, where all 53 flops matched by Q-net: buf_pc, buf_data, nBufValid, …) and on the whole chip (equiv_make paired 642 cones by name across the 61k-cell design). The check is rho-recoverable in check-l3.

This downgrades F5 from the layer's load-bearing unknown to settled in the affirmative. What remains open is not ρ's existence but the equivalence proof that rides on it (04), and the 42-flop residue's per-flop justification. The instrumentation programme below is no longer the primary route — the Q-nets already are the witness — but it survives as the way to certify the 42 anonymous flops and the polarity/constant deviations without leaning on the naming convention.

Why only registers (and ports) need correspondence

The equivalence needs bit-level correspondence at exactly two places: ports (preserved by construction — synthesis cannot rename or drop them) and state elements. Internal nets need none — internal restructuring is precisely what combinational equivalence checking absorbs, and it is where ABC does all its work. So the entire gap between RTL and netlist reduces to one question: do the flops correspond?

The corollary that saves the project from a research problem: do not recover buses. Synthesis flattened every word into unrelated single-bit nets named _1234_; bit-level→word-level lifting is genuinely hard and entirely unnecessary — the word structure comes from the RTL side of ρ, and the netlist side stays bits forever.

What ρ must record

• The bijection, modulo the two legal deviations: constants (opt_dff removes a flop whose input is provably constant — the RTL bit maps to a constant, and the proof that it was constant is part of the certificate) and clones (resizer fanout duplication — one RTL bit, several netlist flops, all provably equal).
• Per-bit polarity — 02's inverter absorption can leave a netlist flop storing the negation of its RTL counterpart.
• Reset correspondence: the bisimulation is stated from reset-reachable states, so ρ must map RTL initial states to netlist post-reset states — with deliberately-uninitialised bits on both sides refining the spec's reset nondeterminism (00) rather than demanding equality of X.

What threatens ρ

Yosys's opt_dff/opt_merge can remove constant-driven flops and merge duplicated ones, and Yosys emits no SVF-equivalent — the commercial flow's hint file recording exactly the register transformations, absent here. The flow's configuration is favourable (retiming off — the one transformation that destroys register boundaries wholesale — and SYNTH_BUFFERING 0), but favourable is not known.

The decision procedure: instrument the synthesis

Do this before anything else in the project. Versions are pinned exactly (the toolchain manifest in findings); Yosys is single-threaded and essentially deterministic; ABC's seeds are fixed by default. Because the flow is re-runnable at will, the experiment is direct: instrument it to dump ρ as it runs — log every opt_dff/opt_merge action, emit the name mapping before mangling — and the witness is an output of the same run that produces the netlist of record. This is also the first concrete instance of the project's endgame — tools patched to emit certificates — arriving early because it needs only logging, not proof.

The nondeterminism concentrates in P&R (multithreaded routing, placement seeds, hash order, floating point), which is function-preserving — a different placement is harmless, and one verifies the layout the flow produced rather than demanding reproducibility of it. Synthesis, the stage that would actually hurt, is the deterministic one. Fortunate, and worth stating as the reason the witness is expected clean.

A determinism check (same run, twice, same netlist) is still worth pinning as a regression: it is what makes "the netlist of record" a well-defined phrase.

Obligations

1. Run the instrumented synthesis; extract ρ; pin the determinism regression.
2. Define the ρ format (bijection + constants-with-proofs + clone classes + polarity + reset map) as the interface 04 consumes.
3. If reproduction fails: fall back to inference — name-hint matching plus simulation-based candidate pairing, then per-pair verification. Strictly worse (the witness becomes a search result), but the verification step is the same either way.

Interface (base case). The reset map recorded in ρ is the S-reset seam: the base case of L3's temporal lift, rename ρ resetF = resetR (reset_corr). It is the one sorryAx in the end-to-end theorem's axiom base — the induction anchor without which the two machines could agree step-for-step yet start from unrelated states. L3/03's "no flop carries a power-up value" is the necessary precursor, not the ρ-image equality itself.

Effort

The experiment: days to weeks of flow wrangling. It is the highest information-per-effort action available in the entire project, which is why the repository README's "where to start" lists it first.

L2/04 — Equivalence by certificate

Background

The question "do these two circuits compute the same function?" — combinational equivalence checking, CEC — is the workhorse problem of hardware verification, and this chapter leans on thirty years of its technology, so the technology needs introducing. The foundation is the SAT solver: a program that takes a Boolean formula and either finds an assignment making it true or reports that none exists. SAT is the canonical intractable problem in theory, but modern solvers (the architecture is called CDCL — conflict-driven clause learning: search, hit a contradiction, learn a clause recording why, never repeat that mistake) routinely dispatch industrial instances with millions of variables. Equivalence reduces to SAT by the miter construction: wire the two circuits to the same inputs, XOR their outputs, and ask the solver whether the XOR can ever output 1. "Unsatisfiable" means no distinguishing input exists — the circuits are equivalent.

Two refinements turn this from possible into practical. First, equivalence tools do not attack the miter whole; they exploit the fact that the two circuits being compared are usually versions of the same design, littered with internal wires that compute identical functions. SAT sweeping finds them: simulate both circuits on random inputs, group internal nodes whose simulated values always agree (candidates), prove each candidate pair equivalent with a small local SAT call, and merge them — so the two circuits progressively fuse from the inputs forward, and no solver call is ever large. (The circuits are held in a normal form called an AIG — and-inverter graph, everything expressed as two-input ANDs plus inverters — which makes structural sharing cheap and mergers mechanical.) The crucial corollary runs backwards: sweeping starves without structural similarity, which is why this chapter insists the right comparand is the RTL that generated the netlist, never an independently written reference model.

Second — and this is the book's recurring trust move, stated here at its origin — a solver's "unsatisfiable" verdict need not be taken on faith. Solvers can emit a proof log (the standard formats are DRAT and its checkable-in-linear-time refinement LRAT): a step-by-step derivation of the contradiction that a small, simple, independently verified checker can replay. The solver stays a wild, heuristic, untrusted search engine; trust resides only in the checker. This search-vs-certificate split is how every SAT-shaped result in the project enters the proof, and this chapter pushes the same idea one level further: the synthesis optimiser's own rewrites are drawn from a finite, pre-verifiable library (the "222 NPN classes" below are the 4-input Boolean functions up to negating/permuting inputs and negating output — a complete catalogue), so if the tool is patched to log which rewrite it applied where, the entire optimisation trail becomes a checkable certificate and search at verification time disappears.

Statement

Given ρ (03) and the deletions (02): for every register/port boundary pair, the combinational cone in the reduced netlist computes the same function as the corresponding cone in the elaborated RTL — established by checking certificates, with exploratory SAT confined to where no certificate exists.

Per-cone equivalence + ρ + matched reset then compose into the bisimulation Mealy(N) ≈ρ ⟦RTL⟧.

Why CEC scales, and why that dictates the architecture

SAT sweeping works by proposing candidate-equivalent internal nodes via random simulation and proving each with a small local SAT call, using previously proven equivalences as rewrites. The candidates exist because both sides are the same design through one tool — structural similarity is the fuel. Two consequences:

• An independent reference model is the wrong architecture. Comparing a hand-written model against a synthesised netlist destroys the internal equivalence points; the miter becomes one enormous SAT problem. (This is quite apart from the register-mapping problem an independent model creates.) The RTL that generated the netlist is the right comparand.
• Register boundaries bound every miter. With ρ in hand, each proof obligation is one cone — an in-order core's are shallow — so even certificate-free fallback SAT stays tractable per cone.

Unmap rather than map: substitute each SKY130 cell's verified Boolean function (L1/06) to bring the hardened netlist down to generic gates, instead of technology-mapping the RTL side up. Free — L0 already produced the functions — and it removes tech mapping from the comparison entirely.

The certificate architecture: instrument ABC's trail

ABC's optimisations are local rewrites drawn from a finite precomputed library — the 222 NPN classes of 4-input functions for rewrite, plus refactor/balance/resub. Every application is a table lookup plus a structural substitution; the justification already exists as a table entry — ABC just doesn't write it down.

The plan, enabled by 03's reproduction of the flow (we control the run, so we can patch the tool):

1. Verify the NPN library once, exhaustively — 222 lemmas over 4-input functions, trivially checkable.
2. Log the trail: (cut, before, after, library-entry) per rewrite — a modest patch to an open-source tool.
3. Check the trail: each step is congruence (substitution at a cut, pointer-level if the representation is a hash-consed AIG (And-Inverter Graph — the two-input-AND-plus-inverter normal form equivalence tools operate on)) plus one library lemma. No search at check time.
4. Residual cones — anything the trail doesn't cover as a pure library rewrite: proc/techmap structural expansion, and ABC's mfs, the flow's only don't-care-licensed pass (measured below). For mfs the trail records each resubstitution with its don't-care condition, discharged by checking that condition or by a windowed SAT-with-DC-assumption; other residue falls back to per-cone SAT with LRAT proofs, checked not trusted.

This is the K(G₁) = K(G₂) congruence architecture the project sketched from the start, landing at its cheapest available site: local rewrites, precomputed justifications, open tool. It is the best available answer to avoid poorly-specified exploratory obligations.

Measured: the don't-care footprint of this flow

The certificate architecture above splits every synthesis rewrite into two bins: exact (a full-input-space Boolean identity over a bounded cut — certifiable locally, by composition, against the finite rewrite library) and don't-care-licensed (the rewritten cut equals the original only on the inputs that can occur (satisfiability DCs) or that are observed (observability DCs) — not certifiable by local pin-projection, because the licensing condition is a non-local property of the surrounding circuit). Only the second bin is the hard residue. So the operational question is: how big is it, on this design? We instrumented the flow and measured it.

The flow's ABC script, classified. The synthesis step hands ABC a script (runs/*/06-yosys-synthesis/AREA_0.abc) of eighteen passes. Every one is exact-equivalence except a single don't-care pass:

• exact — fx (algebraic factoring), strash (structural hashing), drw/drf (rewrite/refactor from the 222-NPN 4-input library), balance (associativity), the fraig_store/fraig_restore sweep (SAT-proven node merges), amap and &nf (technology covering — implement the AIG function by construction), &dch (structural choices — invoked bare, so proven-equivalent snapshots only, no don't-care merge), buffer/upsize/dnsize (function-preserving sizing);
• structural no-ops — retime -M 5, scleanup, and the sequential &get -n path. Yosys runs dfflibmap before ABC, so ABC receives a purely combinational network: its own stats report lat = 0. There are no latches to retime. Flop boundaries — ρ — are fixed before ABC touches anything; the flow performs no retiming at all. This is not a configuration we chose; it is visible in the log (ABC: Error: The network is combinational when retime runs) and it removes register-level non-locality from the problem entirely.
• don't-care-licensed — mfs (and only mfs): SAT-based resubstitution and redundancy removal using satisfiability and observability don't-cares. This is the whole of bin two.

So the design-wide don't-care residue is exactly one pass, and mfs reports its own footprint. Instrumenting it (cec/dc-instrument.sh, cec/dc-fullchip.sh — the flow's script with mfs -v, run pass-by-pass) gives:

Two things fall out. First, the footprint is small and self-reported: mfs names the exact nodes it changed, so the certificate does not have to discover the don't-care residue — the tool hands it over. Every node mfs did not touch is reached by exact rewrites alone and certifies locally.

Second, the genuinely non-local part is almost nothing. mfs's -W flag is the observability (transitive-fanout) cone depth; -W 0 leaves only satisfiability don't-cares, which are a property of a node's fan-in — still non-local, but input-side and bounded by the cone the local cut already sees. Re-running the whole flow with -W 0 reduces the full chip by 4,241 nodes versus 4,249 with observability on: the observability don't-cares — the ones whose licensing truly depends on what the rest of the circuit ignores, and which no enlargement of the local window can ever capture — account for 8 nodes in the entire design. The full 8% is satisfiability-DC. AMOALU shows the same (-W 0 identical, all 28 resubs satisfiability-based). IBuf looks larger (~10 nodes, ~0.8pp) precisely because it is carved out: a module observed only at its boundary has artificial observability don't-cares that vanish once it is wired into the closed chip — the same free-boundary effect as the IBuf reset residual in the Executed runs below, and the reason the honest number is the full-chip one. Observability don't-cares and unobserved boundary state are the same phenomenon seen from two sides, and in the closed design there is almost none of it.

Consequence for the certificate. The trail checker discharges every exact pass locally. For mfs, the trail records each resubstitution with its don't-care condition; the checker either verifies that condition or falls the cut back to a windowed SAT-with-DC-assumption. The measurement says that fallback is invoked on ~8% of nodes — and of those, all but a handful carry a satisfiability condition (which input patterns reach the cut: a bounded fan-in property the windowed check already has in scope), while the observability-dependent part, the only kind that resists any local window whatsoever, is 8 nodes in 52,775. The die-wide CEC does not merely factor into local checks in principle; on this design the non-local remainder is one instrumented pass, over 99.9% of it input-side and windowable, with a hard core of eight nodes.

Executed: re-checking mfs's don't-care SAT calls outside ABC

The measurement says the don't-care residue is one pass and it names its own footprint. The next step is to make that pass hand over the proof obligation it discharged, and re-check it without trusting ABC. We patched ABC to do exactly this (cec/abc-mfs-dclog.patch, ~50 lines; cec/DC-CERT-NOTES.md).

To license each reduction, mfs builds a two-copy care-aware miter (Abc_MfsCreateSolverResub): two copies of the window, tied on the candidate divisors, with the node's output forced to disagree. UNSAT means no two care-set inputs agree on the divisors yet differ on the node — the node is determined by those divisors on the care set — so the reduction is valid; ABC then reads the replacement function off that same refutation by Craig interpolation. The refutation is the certificate. The patch, gated by an environment variable, dumps the complete CNF of that miter (assumptions baked in as unit clauses) for every applied reduction, plus a manifest tying each to its node and window support. An off-the-shelf solver re-deriving UNSAT removes ABC's SAT engine from the trust base for the whole don't-care step.

Run through the flow via abc -exe, then discharged by minisat and z3 (cec/dc-log.sh, cec/dc-check.py):

Coverage is exact at every scale: the dumped remove/replace counts equal mfs's own Remove/Resub accounting to the unit — IBuf 206/174, and the whole chip 2,917/3,255 — so all 2,917 observability-based removes, the genuinely non-local reductions, are among them. Every don't-care SAT call the flow made is reproduced by a solver outside ABC, and every one is UNSAT (a SAT here would be an ABC soundness bug; none occurred).

This discharges the "re-do the don't-care SAT calls" obligation. Two layers remain, and the manifest is built to reach them: emitting a DRAT/LRAT proof from the external solver upgrades each verdict to a checked proof; and mapping the dumped window variables back to netlist nets (the manifest records the support net ids) closes the "faithful window" obligation — that the dumped miter models the real netlist's don't-cares — against 00's semantics. What is already true is the sharp part: the die-wide don't-care residue is one pass, its every reduction is logged as a bounded local refutation, and those refutations check outside the tool that produced them.

The exact passes: per-pass equivalence, checked outside ABC

mfs is the only pass that needs a don't-care argument; every other pass in the script — fx, strash, the rewrite/refactor/balance block, the fraig sweep, amap, &dch/&nf — preserves the function on all inputs, so each is a plain equivalence with no care set. That invites the obvious check: verify each pass against the one before it.

Why per-pass rather than one shot: the monolithic RTL≡netlist miter is exactly the compute-bound object from the runs above — the two sides are dozens of passes apart, structurally dissimilar, so SAT sweeping starves. Consecutive networks are one pass apart and nearly identical, so the same sweeping collapses each adjacent miter in milliseconds. Snapshotting the network after every pass and checking neighbors turns the one hard CEC into a chain of trivial ones — precisely the "trail of intermediate netlists" the certificate architecture calls for, at its cheapest.

cec/trail-cec.sh does this: it snapshots after each pass (&get -n for uniform signal names; s0 via non-destructive write_blif, since fx needs an SOP network), exports each adjacent miter (miter -c, whose single output can be 1 exactly when the two circuits differ), and discharges it with minisat — outside ABC — keeping ABC's own cec as a cross-check. The polarity is falsification-tested (an AND-vs-OR miter yields SAT), so a false "equivalent" cannot pass.

For AMOALU and IBuf, every boundary is independently UNSAT and ABC's cec agrees:

s0_start -> s1_fx      : UNSAT (equivalent)   | abc: are equivalent
s1_fx    -> s2_mfs     : UNSAT (equivalent)   | abc: are equivalent
s2_mfs   -> s3_strash  : UNSAT (equivalent)   | abc: are equivalent
s3_strash-> s4_rewrite : UNSAT (equivalent)   | abc: are equivalent
s4_rewrite->s5_fraig   : UNSAT (equivalent)   | abc: are equivalent
s5_fraig -> s6_amap    : UNSAT (equivalent)   | abc: are equivalent
s6_amap  -> s7_nf      : UNSAT (equivalent)   | abc: are equivalent

For the whole ChipTop, all seven boundaries are equivalent too, each in 0.06–64 s (~3.3 min total) — tractable exactly where the monolithic RTL≡netlist miter is not. The chain composes: s0 ≡ s1 ≡ … ≡ s7, so the pre-ABC network equals the final mapped netlist. The mfs boundary (s1→s2) passes this whole-network check too — it is output-preserving — while its internal don't-care reductions get the finer, per-reduction certificate of the previous section.

One honest scaling seam. On the modules the external solver discharges each boundary; on the full chip the boundaries are checked by ABC's own cec, because a plain external solver does not scale on the raw die-wide miter — minisat exceeds two minutes on a 69k-variable boundary, for want of the structural node-sharing that cec's fraig sweeping supplies and a bare CNF discards. So at full-chip scale this step still trusts ABC's checker (not its optimiser). Closing that — a structure-aware CEC that emits a DRAT/LRAT proof a small checker can replay — is the remaining hardening; the decomposition has already done the hard part, cutting the die-wide problem into seven individually-tractable steps.

So the ABC trajectory is covered end to end: the exact passes by adjacent-miter equivalence (external on modules, ABC-cec in minutes on the die), and the one don't-care pass by both this whole-network check and its 6,172 externally-replayed SAT refutations. What remains is the front end — s0 back to the RTL (proc/techmap structural expansion, the "naive netlist" of the next section) and, above it, L3's elaboration semantics. The ABC middle — historically the heuristic, untrusted part — is now a chain of small equivalence checks anyone can replay.

The naive netlist: useful oracle, wrong comparand

read_verilog; hierarchy; proc; memory_map; techmap — no opt, no abc — produces a "naive" netlist whose function is fixed by the language and whose structure is fixed by Yosys's techmap.v, a small readable rule library one could formalise. Caveats: proc is not a no-op (proc_rmdead prunes unreachable branches), and well-definedness is conditional on L3's 15 always @* latch-inference checks — the obligation is shared between layers.

But as a CEC comparand it is the worst case: its ripple-carry adders share nothing structurally with ABC's output, so sweeping starves. Its role is differential testing and semantics cross-validation (L3's CEC cross-check), not the equivalence proof itself. The trail architecture makes this moot: with the trail, the comparand is each intermediate netlist against the next, and structural similarity is maximal at every step.

Executed: the equivalence check as run

Ahead of the instrumented-trail endgame, the equivalence was run with off-the-shelf machinery (eqy and yosys equiv_*), matching by name via ρ (03) with no hint file, to find out what the obligation actually costs on this design. Three results, one coherent picture.

A cone closes cleanly. AMOALU — the atomic-memory-op ALU, a purely combinational Rocket cone — synthesised standalone to SKY130 cells and checked against its RTL yields Equivalence successfully proven, all 32 output bits. The whole pipeline runs end to end: slang elaboration → standalone synthesis → cells read against Liberty → equiv_make name-match → SAT → proven. This is scoped-cec in check-l3, and it is the proof that the pipeline itself is sound — no confound, a real PASS on real Rocket logic.

A sequential cone exposes the reset issue, not a bug. IBuf (instruction buffer, 53 flops) matched every flop by Q-net and proved 198 of 212 cones on the first pass. The residual is not a logic discrepancy: 115 of the unproven cells are primary outputs driven by the unreset data registers buf_pc/buf_data, whose two copies start at independent free values, so every output that reads them differs at cycle 0. A carved-out module observed at its boundary from an arbitrary state genuinely is not output-equivalent; the correct statement is equivalence under matched initial register state — ρ as an assumed initial condition, standard SEC practice — which needs the reset sequence modelled. The matching (F5) is untouched; what is open is a clean whole-module sequential verdict.

The whole chip confirms matching but not a clean verdict — by either route. eqy's per-flop partitioning matched ~10,900 cones by name (ρ at full scale) but its serial combine is a multi-hour grind. The yosys-native single-miter route (equiv_make/equiv_simple/equiv_induct) matched 642 cones by name, but equiv_simple proved only 6 of them — the same free-register-init wall as IBuf, dominating even the combinational check when the whole design's registers start free — and equiv_induct exhausted memory without closing. So a clean full-chip number needs either the per-partition route run to completion (compute) or reset-sequence modelling (the IBuf lesson at scale). The scoped AMOALU pass remains the standing evidence the pipeline is correct; the full-chip verdict is cec-fullchip, still open, and blocked on compute/reset-modelling rather than on any doubt about the method.

The lesson for the architecture below: matched-reset (the ## Statement's hypothesis, and 03's reset-correspondence clause) is not a formality — it is exactly what these runs show is needed to turn per-cone combinational equivalence into a whole-design verdict. The certificate route inherits the same requirement; the trail proves the cones, and the reset correspondence composes them.

Obligations

1. The NPN library verification (one-time, mechanical).
2. The ABC patch and trail format; the trail checker against 00's semantics.
3. The composition theorem: per-cone equivalences + ρ + reset correspondence ⟹ bisimulation.
4. LRAT checking for residual cones — standard machinery, imported not built.

Interface (trust anchor). The soundness of these certificates is the S-miter seam (miterCNF_sound): that the miter CNF faithfully encodes inequivalence, so a refutation proves the machines equal. It is the one seam that is not an inter-layer arrow but a trust anchor — every PassCert and l2_commutes rest on it — and the one dischargeable outright: a verified Tseitin encoding turns it from axiom into theorem.

Effort

The patch and checker: months. The composition theorem: weeks once 00/03 exist. The certificate route's cost scales with the trail length, not the design size — which is the point.

L2/05 — Hard cones and the transformation contingency table

Background

Equivalence checking has one famous nemesis: the multiplier. For most logic, the SAT-based machinery of 04 is robust, but comparing two structurally different multiplier implementations — say, a naive shift-and-add against a Booth–Wallace array (the standard fast architecture: recode the multiplier digits to halve the partial products, then sum them through a tree of carry-save adders) — is provably brutal: the XOR-rich structure of binary arithmetic is exactly what the resolution proof system underlying SAT solvers handles exponentially badly, so the miter that "should" be easy runs forever. The field's dedicated answer is algebraic rather than Boolean: model each gate as a polynomial equation and verify, by systematic polynomial reduction (computer algebra, not SAT), that the circuit's output polynomial equals a·b; the PAC format packages such reductions as certificates a small checker can replay, SAT's LRAT story transplanted to polynomial arithmetic.

This chapter's actual claim is that the famous problem does not arise here — for a structural reason worth spelling out. The wall is triggered by comparing structurally alien endpoints with no shared derivation. But the hardened netlist's arithmetic was not conjured from nothing: Yosys elaborates the RTL's + into a width-generic template — a recursive circuit definition parameterised by bit-width, the "circuit generator" of this project's earliest design discussions — and ABC then only massages that structure through small local rewrites, each logged in 04's trail. So the proof splits into one induction over the template ("for every width n, the template computes addition" — a textbook induction on the carry recurrence, proved once for all instances) plus the per-rewrite trail checks, and no alien-endpoint comparison ever happens. The PAC machinery stays shelved as a fallback.

The chapter's second half guards a different flank: synthesis transformations that would break the register correspondence ρ wholesale. Retiming is the canonical one — moving flops across combinational logic to balance delays, perfectly sound and perfectly destructive of any flop-to-register mapping. Others (re-encoding an FSM's states, merging equal registers, inserting scan chains — the test-mode circuitry that threads all flops into a shiftable chain for factory testing) each break a different assumption the equivalence proof rests on. This flow has all of them switched off; the table's job is to convert "switched off" from a configuration hope into a checked property of the reproduced build, with a named certificate ready should any of them ever appear.

Statement

Two residual categories where 04's architecture needs reinforcement: cones where SAT structurally blows up (arithmetic), and synthesis transformations that break register boundaries (absent from this flow, but each needs a named certificate so their absence is a verified configuration, not luck).

Arithmetic: generic theorems, not SAT

The plan for arithmetic cones is width-generic structural proof, with per-instance checking confined to the local peepholes on top. The emitted cone descends from the RTL operator with full structural continuity:

RTL +/*  —elaborate→  $add/$mul  —techmap→  template structure  —ABC→  hardened cone
                                  └─ width-GENERIC theorem ─┘    └─ 04's local trail ─┘

The middle step is Yosys's techmap.v / alumacc instantiating a width-generic template — a recursive structure over n. ∀n. ⟦template_add(n)⟧ = bvadd_n is a textbook induction on the carry recurrence, proved once, covering every instance at every width; likewise the other $alu/$macc templates. We do not own the generator, but the generator is small, fixed, pinned Verilog — the generic-generator proof from the project's original design discussions, in validation form. Identifying which templates the pinned Yosys uses is a deliverable of 03's reproduction. The final step is ABC's cut-local rewrites — 04's trail; each check is a 4-input peephole, never a multiplier.

The "multiplier wall" is not intrinsic to arithmetic — it is intrinsic to endpoint-vs-endpoint comparison of structurally alien implementations (bit-blasted * against a derivation-free Booth–Wallace array: exponential resolution, sweeping starves). With template theorem + trail, that comparison never occurs. PAC (Kaufmann & Biere) — polynomial-calculus certificates with a small verified checker — is therefore the fallback, earning its place only on trail loss or on a structurally alien vendor block with no derivation history; this flow has neither.

The multiplier case factors completely: this core's multiply/divide unit is iterative (the tiny configuration's M implementation), so correctness splits into an RTL-level loop invariant (standard, L4/L5's world) plus a step-function cone that is an adder: generic theorem + trail. The scary version of this problem belongs to cores with single-cycle combinational multipliers, not to this one — and the configuration parameter that keeps it iterative is pinned in the configuration record precisely so a change is noticed as a re-budgeting event.

The contingency table: boundary-breaking transformations

The flow's configuration avoids every transformation that destroys register correspondence (Findings: retiming off, SYNTH_BUFFERING 0, no sequential optimisation flags). Under unbounded proof capacity none of them are forbidden — each admits a certificate — and the table's job is to make "we don't need this machinery" a checked property of the reproduced flow rather than an assumption:

Each row is a known technique with literature behind it; none is exploratory. The point of writing them down is asymmetric risk: discovering mid-proof that the flow did apply one of these without a witness would invalidate ρ silently — so 03's instrumented reproduction should also assert the absence of each row (grep the flow's pass list), converting the table from contingency to certificate-of-absence.

Obligations

1. Identify and generically prove the pinned Yosys arithmetic templates (techmap.v, alumacc) — one induction per template, the load-bearing item of this file.
2. Confirm the mul/div unit's iterative parameters from the configuration record; state the loop invariant and check the step cone reduces to the adder template.
3. Emit the certificate-of-absence for the six rows from the reproduced flow's logs.
4. Import a PAC checker (Pacheck-class) rather than building one — same policy as LRAT — and keep it shelved unless the trail is lost.

Effort

Weeks, dominated by wiring the PAC checker to 00's cone extraction — needed only if the template-plus-trail route fails somewhere.

L1 — The electrical circuit and its constraint system

Node — the EE circuit and its constraint system: the extracted netlist N with per-net RC enclosures (00–02), the timed contract model (03), the SDC constraint set (04), and the crosstalk/IR budgets (05); at this node ε has been traded for a deterministic constraint system. Edge up — the digital crossing: timing closure, the combinatorial geometry/interference checks, and gain-driven restoration together turn the transfer functions into a Boolean machine Mealy(N) — the digital abstraction (06), the bridge theorem (07), verified STA (08), corners (09), the clock (10), boundaries (11), and the geometric checks (12). This edge carries the second of the overview's two † conditioning marks (P1).

This layer is the merge of two bodies of work that share one object. The geometry half (00–02, and its continuous-field enclosures, which live in L0's electrical-abstraction edge) is what defines the EE circuit: the drawn polygons realise exactly the intended netlist, for every chip in the tolerance family, and extraction reads the circuit back out with certified RC. The timing half (03–12) is the digital crossing: given that circuit, the synchronous discipline lifts it to a discrete machine. The node is the circuit; the edge up is the crossing.

Background

The design is a stack of 2D polygon layers; the chip is what a fab printed from them — imprecisely, but within published tolerances. The first job of this layer is to connect the two: the drawn geometry realises exactly the intended circuit, for every chip in the tolerance family rather than the ideal one. The sandwich theorem (01) is what makes design-rule checking on the drawing sound for the fabricated silicon; extraction and LVS (02) read the circuit back out of the polygons; the capacitance enclosures (09) turn geometry into certified electrical intervals; the screening argument (10) is the open problem that makes any of that computable at all; and the geometric checks (12) discharge safety conditions that other layers can only state. 00 opens with how a chip is physically built and what a layout formally is.

The second job is the digital crossing. Everything above this layer treats the chip as a discrete machine stepping once per clock; the circuit this layer defines is a continuous system in which signals race through gates at analog speeds and arrive when they arrive. The synchronous discipline — storage elements that sample only at clock edges, given a full period for the racing to settle — is what connects the two pictures, and the edge up proves that it does: the bridge theorem (07) turns "the design meets timing" into "the discrete abstraction is sound," checked by a verified static timing analysis (08) over certified delay tables (09), conditional on the human-asserted path exceptions being justified (04). The edges of the story get their own chapters: the clock's generation and distribution (10), the boundaries where the world's timing meets the chip's (11) — one of the two places genuine probability enters the project — and the analog interference terms kept out of every interface (05).

The node: the EE circuit

One theorem with three faces defines the circuit, decomposed in the geometry subcomponents:

1. The layout implements the netlist. Ext(M(A)) ≅ N for all A in the family — the sandwich theorem (01) plus extraction/LVS (02).
2. The layout determines RC enclosures, valid over the whole family (09, 10).
3. DRC rules are the hypotheses, not an unstructured pile of manufacturing constraints — (H1)(H2), (D1)–(D3), G1–G6.

On top of that geometric netlist sits the constraint system that replaces ε with something deterministic: each cell carries its timed contract (03), the design carries an SDC — the human-asserted timing exceptions (04) — and the analog residue (crosstalk, IR drop) is absorbed as budgets with a single entry point (05). This is the largest and least-charted node in the tower. On the FPGA alternative the geometry half disappears entirely; the timing half remains.

The edge up: the digital crossing

The bridge theorem. If every cell stays inside its contract's domain, STA certifies setup and hold at every flop at every corner, every excluded path carries a justified exception, the combinatorial geometry checks discharge L0's interference budgets, and no fault event or unresolved synchroniser read occurs in [0,T] — then over [0,T] the physical circuit implements Mealy(N). Full statement and proof sketch in 07; the hypotheses are not yet established for this design — the flow's multi-corner signoff is the F-series' live frontier (axioms).

The crossing has three ingredients, all of the same "combinatorial check over an analog budget" flavour: timing closure (clean sampling instants), the geometry/interference checks (12, discharging L0's budgets), and restoration (gain > 1 collapses each cell's transfer function to a Boolean function — the digital abstraction, 06, which migrates up from the physics). Everything above L1 presupposes this edge and nobody has written it down. It is the highest value-per-effort novel contribution in the project.

Subcomponents

The continuous-field enclosures the geometry face depends on — the two-sided capacitance bounds (09) and the screening exponent (10) — now live in L0's electrical-abstraction edge, because they are analog field arguments; L1 consumes their intervals.

Interfaces

Consumes: GDS, process stack, DRC deck; from L0, the per-cell interval Liberty contracts and the RC enclosures + coupling graph that make up Contracts(N); from L2, the netlist with registers/clock/reset identified; the generated SDC. Exports: the netlist N — the shared object of the overview's tower, the same N this layer times and L2 compares — with per-net RC enclosures and a sparse coupling graph plus one aggregate ε; and, from the edge up, the licence to reason discretely — for the multi-domain design a network of Mealy machines with gadget-bounded channels (11) that collapses to nearly one machine here. Nothing numeric propagates upward except one outward artifact: the derived AC-timing table handed to L5.

The refinement proof never touches RC. Electrical data exists solely to discharge the digital crossing's hypotheses — the cleanest seam in the stack, preserved deliberately: any net that would need a functional coupling constraint is a layout bug, because it would entangle the noise argument with L3's invariant (05).

Axioms introduced

From the geometry face: E7 (as-fabricated geometry within the tolerance family — now also carrying the sandwich's (H3)), P4 (variation within corners), P5 (defect coverage), X3 (T→theorem: retires when M2 lands). From the edge up: P1 (synchronisers resolve — the per-boundary ledger is 11's), P6 (environment — now carrying the whole clock-generation contract, since the clock is board-supplied, 10). Formerly also E3 (discharged — the capacitance enclosures are its route), E6 (retired: yield, not per-die correctness), E4 (split: empirical half → P4, mathematical half → M4), and E5 (subsumed by E2's and E3's discharge routes); see Axioms. The F-series rows are unestablished hypotheses of the bridge theorem, not axioms.

Two things precisification turned up

The sandwich theorem needs a third hypothesis. With only "erosion connected" and "dilations disjoint" it is false: the fabricated set may contain a spurious island inside N ⊕ B_r that meets no eroded net, i.e. a net that does not exist in the drawn layout. The missing hypothesis (H3) — every component of Cond(A) meets Cond(D) ⊖ B_r — is not checkable, since it quantifies over A. It is an assumption about the process and belongs to E7. (No dual hypothesis is needed for voids: extra material creates nets, missing material cannot destroy them, because the eroded net is already connected.)

01's conclusion overclaims. Its statement says the net bijection preserves device-terminal incidence, but its proof handles only nets. Devices are components of poly ∩ active and perturb under their own sandwich; the missing device-level hypotheses (D1)–(D3) are stated in 02. (D3) — terminals stay attached — is exactly where line-end pullback bites, so the enclosure rules are its hypotheses, not the net-level theorem's.

Established during scoping (the geometry face)

The right model of a layout is a coloured image plus a fixed z-extrusion.

d = F(L)                          derived layers; F = booleans + morphology
c : ℝ² → 2^Layer                  pointwise colour
M : ℝ³ → Material,  M(x,y,z) = Z(c(x,y), z)

This is literally what DRC/extraction decks compute (gate = poly AND diff). Two refinements: the algebra is booleans plus morphology (grow/shrink), because self-alignment and diffusion mean the doped extent is the boolean then sized; and the vertical stack is a process constant, which is exactly why a finite extraction pattern library is possible at all. If z varied per design, no library would exist.

The model is exact for interconnect, lossy for devices. BEOL is conductors and dielectrics in fixed geometry — R and C are functionals of M via Laplace, nothing lost. FEOL doping is a continuous 3D concentration profile; the colour only identifies that there is an NMOS here, and (W,L) come from geometry while behaviour comes from a fitted compact model. So verified extraction is available for interconnect and not for devices.

The morphological sandwich, and why DRC is a theorem's hypotheses.

∀ mask m:  erode(D_m + d_m, r_m) ⊆ A_m ⊆ dilate(D_m + d_m, r_m),  |d_m| ≤ overlay_m
           r_m = bias_m(density) + k·σ_m

(a) ∀ nets n: erode(D_n, r) connected              [min width, neck/notch rules]
(b) ∀ n≠n':  dist(D_n,D_n') ≥ r + r' + overlay     [colour-aware spacing rules]
(c) ∀ vias:  enclosure ≥ pullback + overlay        [enclosure rules]
⟹ connectivity_graph(A) = connectivity_graph(D)

Proof is one line each way (erosion spans the net ⟹ connected; dilations disjoint ⟹ no shorts). Min-width and min-spacing rules are precisely (a) and (b). This is self-contained computational geometry — no PDEs, no Sobolev spaces — and converts a large fraction of a DRC deck from folklore into hypotheses. If one piece of the geometry face is formalised first, it should be this.

Caveats: bias is density-dependent so r = r(x); line-end pullback and corner rounding are systematic and are why (c) exists; vias are the dominant open mechanism and are not bounded in-plane at all; multiple patterning makes overlay a rigid per-mask displacement, a different perturbation class, hence colour-aware spacing.

Sub-resolution mask features do not transmit — lithography is a low-pass filter. A gap much smaller than the resolution limit prints as a slight narrowing or nothing. Proof that this is real: sub-resolution assist features work precisely by not printing. So the geometry family to propagate is band-limited, not arbitrary polygon perturbation. Another restoration-like property.

LER does not sever wires; defects do. Severing requires roughness to consume the full width — Gaussian-tail suppressed. The sandwich with r = bias + 4σ is effectively deterministic. Topology changes are Poisson defects handled by test (P5). Same continuous/discrete split as L0.

Extraction is pattern matching against a field-solver-characterised library — template matching on cross-sectional images, with the rule deck as a trained model. The replacement is rigorous enclosures: Dirichlet principle gives upper bounds from any trial potential, Thomson's principle gives lower bounds from any trial flux field, so any pair of trial fields yields a two-sided bracket. Verified-numerics machinery for elliptic BVPs is mature (Nakao, Plum, Watanabe). And the accuracy requirement is soft: ~5% vs field solver, against 10–20% derates already carried — so crude-but-rigorous bounds suffice, which is unusual and makes this viable.

2D may be exactly solvable. Schwarz–Christoffel mapping gives closed-form multiconductor capacitance for piecewise-linear 2D cross-sections in terms of elliptic integrals; verified numerics then only handles the 3D corrections. Better decomposition than treating everything as a 3D PDE.

Corner singularities are the real obstacle. Charge density diverges like r^(−1/3) at a right-angle conductor corner, exactly where the capacitance concentrates. Exponents are analytically known, so graded meshes work — but verified quadrature must handle integrable singularities.

You want enclosures over a geometry family anyway. As-fabricated ≠ drawn (etch bias, LER, CMP). So the right object is "∀ geometries within tolerance, C ∈ [lo,hi]" — which interval methods give naturally and which is arguably more faithful than the point-geometry field solve it replaces.

Below extraction it becomes image processing for real: DRC is polygon booleans; LVS is extraction + graph isomorphism; OPC is literal inverse imaging (simulate partially-coherent image formation, iteratively adjust mask polygons); fracturing is rasterisation, and multi-beam mask writers take a bitmap. Note E7 sits between LVS and the fab: the mask is deliberately not the drawn layout, so LVS-verified geometry is not what prints.

GDS is a clean formal object with dirty corners. A finite set of layer-tagged integer-coordinate polygons plus a hierarchy — far cleaner than Verilog. But: layer numbers are semantically empty (need an external layer map); PATH endcap type 1 is a semicircle so the format isn't purely polygonal; self-intersecting polygons and same-layer overlap semantics are unspecified. Restrict to a well-formed subset. Encouragingly, OpenROAD-era routing streams out as BOUNDARY polygons — so production output lives in a much cleaner subset than the format permits (pinned per layout by the checker).

The geometric combinatorial obligations

L1 owns a set of finite, decidable checks — the discharge points for conditions L0's operating envelope only states (L0/06 has the dispatch table). These are the combinatorial, relational geometry (spacing, taps, "≥ N apart") that make up the geometry ingredient of the digital crossing, as opposed to the continuous field geometry that stays in L0's edge. Stated precisely as G1–G6 in 12: tap coverage, ECC interleaving, antenna ratio, width/spacing/enclosure, shielding coverage, and tied fill.

Two of the six are not properties of the geometry alone — interleaving needs the ECC word structure from L3/L5, and the antenna check quantifies over prefixes of the process order rather than over the finished layout. That is worth carrying as a general caution: some geometric obligations need inputs a layout tool does not record.

The recurring structure, seen from this layer

Three of the project's global patterns surface here in their sharpest forms. The clock edge is a restoration point in time — the induction invariant is fully re-established every cycle, so nothing accumulates (07). The boundary gadgets are phase restorers — the window hypothesis is manufactured on-die, never imposed on the world (11). And the analog residue is confined to single entry points: the power grid enters once as an impedance bound, coupling enters once as an interval widening plus a geometric rule (05) — with the red line that any net needing a functional coupling constraint is a layout bug.

Open problems

From the geometry face:

1. The screening exponent — the load-bearing open problem of the geometry face. The far-field coupling sum does not obviously converge: the count of nets at distance d grows polynomially while unscreened coupling decays only logarithmically. Truncation is justified not by "distant things are small" but by screening making the decay fast enough. The mechanism is a mesh of apertures in series, giving multiplicative attenuation and hence C_far(d) ≲ C_adj · α^(d/p) — exponential in grid cells traversed. The rigorous object is harmonic measure of the aperture set, bounded via the maximum principle (complete enclosure ⟹ exactly zero; this case is topological, not metric, and so combinatorially checkable). Deriving α is a genuine analysis problem and everything in local extraction depends on it (10).
2. Formalising the variational characterisations of capacity — Sobolev machinery, well outside current Mathlib-scale infrastructure.
3. Verified quadrature with r^(−1/3) singularities.
4. Whether metal fill must be tied rather than floating: floating conductors do not screen, they relay, shortcutting an aperture chain. Should be a requirement, not an option.

From the edge up:

5. Write the bridge theorem (07) — bounded-delay model, window rule, per-cycle induction, multi-domain composition (11).
6. A verified STA engine with the three soundness deviations (08): four-corner interpolation, slew intervals, in-pass domain checks.
7. Prove the constraint set complete — every domain declared or its absence a named finding (04).
8. The monotonicity census and the tier model (09) — decides whether M4 is a footnote or a project.

First experiments

This layer holds the whole project's tractable entry point — 04's work plan: census the domains, diff against the generated constraints, and complete or record each gap. Weeks, needs only the flow's own artifacts, and either outcome is worth having. Alongside it, two mechanical censuses that other files consume: library-wide table monotonicity (08/09) and the clock-network cleanliness check (10).

On the geometry face:

• Formalise the sandwich theorem. Self-contained, no analysis, converts DRC into hypotheses. Highest value per effort in the geometry face by a wide margin.
• Run magic/netgen LVS on inv_1 and check the extracted netlist against the intended one; measure what a per-cell LVS obligation costs.
• Sanity-check the screening claim numerically on a toy 2D mesh before committing to open problem 1.

Effort

3–5.5 years for the merged layer: 2–4 years for the geometry face (the widest error bars in the project — open problem 1 could be six months or could be a thesis; the FPGA alternative deletes it entirely) plus 1–1.5 years for the edge up (the theory concentrated in the bridge theorem and the digital abstraction, the rest verified-algorithm work and measurement). The entry-point experiments are weeks.

Reading

Pólya & Szegő, Isoperimetric Inequalities in Mathematical Physics (1951) — rigorous capacity bounds. Nakao, Plum, Watanabe, Numerical Verification Methods and Computer-Assisted Proofs for PDEs. Driscoll on Schwarz–Christoffel. Lööw's HOL4 Verilog semantics and the Silver/Lutsig stack — closest prior art for a verified path from RTL to netlist; note it stops short of the bridge statement. Standard STA texts for the algorithm — none state the soundness bridge. McGeer & Brayton for the false-path/viability criterion (04). Zgliczyński, Galias, Demir–Mehrotra–Roychowdhury for 10's oscillator contract; Marino for why 11's ε is irreducible.

L1/00 — The layout as a formal object

Background

A chip is built, not carved: it starts as a blank silicon wafer and grows upward through a few dozen processing steps, each one adding, doping, or removing material across the whole wafer at once. The repeating move is photolithography: coat the wafer with a light-sensitive resist, project a pattern onto it through a mask (a stencil, one per patterned step), develop away the exposed resist, and then let the step's real action — etching material away, implanting dopant atoms, depositing metal — act only where the resist is gone. Repeat per layer: first the transistor-forming layers (doped wells in the silicon, the active/diffusion regions, the polysilicon gate material), then, above them, an alternating stack of insulating oxide and patterned metal wiring — met1 through met5 on this process — with vias (small holes filled with metal) connecting one metal level to the next.

The consequence for formalisation is happy: since every step is controlled by a 2D stencil, the entire design content of a chip is a finite stack of 2D polygon sets — one set per layer. That is literally what the design file contains: GDS, the format handed to the mask shop, is a list of polygons with integer coordinates (in database units of 1 nm here), tagged by layer number, organised in a hierarchy of reusable cells. The third dimension is not in the file, because it is not the designer's to choose — the vertical structure (layer thicknesses, what material ends up where when layers overlap) is fixed by the fabrication recipe, identical for every design on the process.

The formal picture this chapter builds is therefore: a drawn layout is a map from layers to polygon sets; a point of the plane has a "colour" — the set of layers covering it; and the process turns colours into materials via a fixed vertical profile, yielding the 3D material distribution that the physics layers below actually analyse. Two further wrinkles the definitions must carry. Some process layers are not drawn directly but derived from drawn ones by boolean combinations and small resizings (the rule deck — a program, supplied by the foundry, that this chapter must treat as part of the spec). And connectivity — which metal shapes form one electrical net — is genuinely three-dimensional, established through vias, so it can only be computed on the assembled stack, never per layer.

Statement

Fix the objects every other L1 theorem quantifies over: what a layout is, what the process turns it into, and which GDS files are admissible.

Nothing here is deep. It is written out because every subsequent statement — the sandwich theorem, LVS, the capacitance enclosures — is a claim about these objects, and they are currently defined only by the behaviour of tools.

Definitions

Layers. A finite set 𝓛, with a distinguished mask assignment col : 𝓛 → Masks (multiple patterning; singleton in the SKY130 case).

Drawn layout. D : 𝓛 → 𝒫(ℝ²), each D_ℓ a finite union of simple polygons with vertices in (δ·ℤ)² where δ is the database unit (exactly 1 nm in SKY130 — measured, Findings). Obtained from GDS by flattening the SREF/AREF hierarchy.

Colour. c_D : ℝ² → 2^𝓛, c_D(x) = {ℓ : x ∈ D_ℓ}. Finitely many values, and only a small subset of 2^𝓛 is realised — the "sparse colouring" of the coloured-image model.

Derived layers. d = F(D) where F is generated by boolean operations and morphology (⊕ B_s, ⊖ B_s). Morphology is not optional: self-alignment and diffusion mean a doped region is a boolean expression then sized. F is the rule deck; it is a program, and formalising L1 means formalising the fragment of it the design uses.

Material distribution. With a process z-profile Z : 2^𝓛 × ℝ → Material,

M(D) : ℝ³ → Material,     M(D)(x,y,z) = Z(c_{F(D)}(x,y), z)

This factorisation is the whole reason L1 is tractable: Z is a process constant, identical for every design on the node, so the extraction pattern library is finite and the design variable is purely the 2D colouring. If Z varied per design, no library could exist. (Second-order caveat: CMP makes thickness density-dependent, so Z carries a correction term depending on local pattern density — see 12.)

Conductive set. Cond(D) = M(D)^{-1}(conductor) ⊆ ℝ³. Nets are its connected components — note this is genuinely 3D connectivity, through vias; the per-layer 2D picture does not determine it.

Admissible GDS

The format permits objects with no agreed meaning. Restrict to a well-formed subset and say so, rather than inheriting tool-specific conventions:

Encouragingly the restriction is expected to cost nothing in practice: OpenROAD-era stream-out emits BOUNDARY polygons for routing, so production output lives in a much cleaner subset than the format allows — a claim the layer's checker pins per layout. The hand-drawn library cells do use PATH (2 in inv_1), so the polygonalisation question is confined to ~400 small files.

What is not determined by D

Worth listing, because these are the inputs to every later theorem and each is an axiom or a separate model:

• Z, the z-profile — process constant, empirical (part of E7's context).
• r_ℓ, the perturbation radii — bias + roughness, density-dependent (E7).
• d_m, the per-mask overlay — rigid displacement per mask (E7).
• ε, the permittivity field — a material property, measured (feeds 09).
• The process order — which matters for the antenna check, which quantifies over prefixes of the build sequence rather than over the finished layout.

Obligations

O1 (flattening). Hierarchy flattening is correct: c_D computed from the flattened polygon set equals the one computed compositionally. Mechanical, but note that abutted cells' wells and implants deliberately merge — inv_1's bbox is 1.760 × 3.100 µm against a 1.380 × 2.720 µm cell boundary — so the colouring of a row is not the disjoint union of its cells' colourings. Composition needs a merging lemma, not conjunction.

O2 (rule-deck fragment). F restricted to the operations the deck actually uses is well-defined and monotone where claimed.

O3 (finiteness). c_D takes finitely many values and each level set is a finite union of polygons — so all downstream quantification is over finite structures.

Effort

Small, and it is the prerequisite for everything else in the layer. Weeks for the definitions; the rule-deck fragment (O2) is the only part that could surprise.

L1/01 — Topology preservation (the sandwich theorem)

Background

The fabricated chip is not the drawn one. Printed features come out with rounded corners and shifted edges: optical diffraction blurs the pattern (at 130 nm the features are already smaller than the light's wavelength), etching eats slightly under the resist (bias), the edges are rough at the nanometre scale (LER, line-edge roughness), and each mask is aligned to the layers below it only within a mechanical tolerance (overlay). None of this is failure; it is the process working as specified, with every effect bounded by numbers the foundry publishes. The question with everything riding on it: under exactly these bounded distortions, does the printed chip still have the same circuit — the same nets, connected the same way, touching the same transistors — as the drawn one? A distortion that merely moves capacitances slightly is absorbed by analysis intervals; one that severs a wire or bridges two nets produces a different machine.

Industry's protection is the design rules: the foundry's rulebook of geometric minima — wires no narrower than this, no two shapes closer than that, this layer overhanging that one by so much — mechanically checked over the whole layout by DRC (design rule checking), with a clean run required before fabrication. The unstated belief connecting the two: pass DRC on the drawing, and the printed version is topologically identical to the drawing. That belief is a theorem nobody has written — the book's flagship instance of "a design rule is secretly a hypothesis of a theorem nobody wrote" — and this chapter writes it.

The mathematics that fits is mathematical morphology, the calculus of dilating and eroding shapes. Dilation (X ⊕ B_r) grows a shape by radius r — everything within distance r of X; erosion (X ⊖ B_r) shrinks it — the points still inside X even after retreating r from every boundary. These two operators turn "the fab prints imprecisely, but by at most r" into a clean two-sided containment — the fabricated shape is sandwiched between the drawn shape eroded and the drawn shape dilated — and turn the design rules into statements with exact roles: minimum spacing guarantees dilated shapes of different nets cannot meet (no bridging), minimum width keeps eroded shapes from vanishing (no severing) — though, as the proof discovers, width alone is not quite enough, and the humble notch/neck rules turn out to be load-bearing. The theorem's payoff is the licence the entire industry already uses daily without stating: geometric checking performed on the drawn polygons soundly certifies the fabricated chip.

Why this one first

It is the only major L1 result that is self-contained computational geometry — no PDEs, no Sobolev spaces, no empirical models — and it is what licenses the entire geometric verification flow: run LVS and DRC on the drawn layout, conclude about the fabricated one. Every EDA flow relies on that inference and none states it.

Writing it precisely turned up a missing hypothesis. See the island problem.

Notation

Minkowski operations on X ⊆ ℝ³, with B_r the closed ball:

erosion    X ⊖ B_r = { x : B(x,r) ⊆ X }
dilation   X ⊕ B_r = ⋃_{x∈X} B(x,r)

Two facts do the work. Dilation distributes over unions, (⋃Xᵢ) ⊕ B_r = ⋃(Xᵢ ⊕ B_r) — this drives separation. Erosion does not; it distributes over intersections — which is exactly why connectivity is a hypothesis and not a consequence.

The perturbation model

D drawn (00), A as-fabricated. Per mask m: a rigid overlay displacement d_m and a radius r_m = bias_m(density) + k·σ_m.

(P)   ∀m:   (D_m ⊕ d_m) ⊖ B_{r_m}  ⊆  A_m  ⊆  (D_m ⊕ d_m) ⊕ B_{r_m}

Write r = max_m r_m and let Cond(·) be the conductive subset of the induced material distribution, so (P) lifts to Cond(D) ⊖ B_r ⊆ Cond(A) ⊆ Cond(D) ⊕ B_r.

Theorem

Let N₁,…,N_k be the connected components (nets) of Cond(D). Assume

• (H1) ∀i: Nᵢ ⊖ B_r is nonempty and connected
• (H2) ∀i≠j: dist(Nᵢ, Nⱼ) > rᵢ + rⱼ + |d_{m(i)} − d_{m(j)}|
• (H3) every connected component of Cond(A) meets Cond(D) ⊖ B_r

Then for every A satisfying (P) there is a bijection ν from nets of Cond(D) to nets of Cond(A) with Nᵢ ⊖ B_r ⊆ ν(Nᵢ) ⊆ Nᵢ ⊕ B_r, and ν preserves incidence with device terminals.

Proof

1. By (H2) the dilations Nᵢ ⊕ B_r are pairwise disjoint.
2. Cond(A) ⊆ Cond(D) ⊕ B_r = ⋃ᵢ(Nᵢ ⊕ B_r) by distributivity. Since the parts are disjoint, every connected component of Cond(A) lies wholly inside exactly one Nᵢ ⊕ B_r.
3. By (H1), Nᵢ ⊖ B_r is nonempty, connected, and contained in Cond(A); so it lies in a single component, call it ν(Nᵢ), and by 2 that component is inside Nᵢ ⊕ B_r.
4. Injective: distinct i give components in disjoint dilations.
5. Surjective: by (H3) each component of Cond(A) meets some Nⱼ ⊖ B_r; by 2 it lies in a unique Nᵢ ⊕ B_r; disjointness forces i = j; so it is ν(Nⱼ). ∎

The island problem

Without (H3) the theorem is false. Steps 1–4 go through and give an injection, but not a surjection: A may contain a component sitting inside Nᵢ ⊕ B_r \ (Nᵢ ⊖ B_r) — a sliver of spurious material — which is a net that does not exist in the drawn layout. The sandwich (P) does not forbid it, because it constrains only containment, not the boundary's shape.

Two ways to repair, and the choice matters:

• (i) Assume (H3). Clean, and honest about what it is: a claim that the process does not create spurious material. It is not checkable — it quantifies over A, which you do not have. So it belongs to E7, and this is a genuine sharpening of E7's content.
• (ii) Strengthen (P) to an edge-displacement model — ∂A is a graph over ∂D, each boundary point moved along the normal by ≤ r. This implies (H3) and is physically the right model (etch and litho move edges; they do not nucleate islands). Cost: it needs a normal field, hence regularity of ∂D, which polygons with corners do not have without care.

Recommendation: take (i), and cite (ii) as the physical reason (i) is true.

No dual hypothesis is needed for voids. A spurious hole cannot disconnect ν(Nᵢ), because ν(Nᵢ) ⊇ Nᵢ ⊖ B_r, which (H1) already makes connected. The asymmetry is real: extra material creates nets, missing material cannot destroy them.

Which DRC rules are which hypothesis

Sharper than the README's earlier claim that "min-width and min-spacing are precisely (a) and (b)":

(H1) is not min-width. Erosion of a connected set need not be connected — a dumbbell erodes to two blobs. Min-width w > 2r makes the erosion locally nonempty; it does not keep it connected across a neck. Notch and neck rules are exactly the missing content, and this is the precise sense in which they are load-bearing rather than cosmetic.

(H2) explains colour-awareness for free. The overlay term is |d_{m(i)} − d_{m(j)}|, which vanishes when the two features share a mask — same-mask features move together. Different-mask pairs need the full overlay budget. That is precisely why multiple-patterning decks carry colour-aware spacing rules, and here it falls out of the statement rather than being a separate convention.

Checkability

So the theorem has two checkable hypotheses and one assumed one, and it is worth stating in exactly that form: conditional on E7, geometric checking on D is sound for A.

Caveats

Vias are not covered, and they are where the failures are. The theorem is 3D so vias participate in Cond, but the perturbation model (P) is an in-plane edge displacement. A via failure is a fill/void phenomenon in z — not an edge moving — so it is outside (P) entirely. Incomplete via fill is the dominant open mechanism in real chips. A separate model for vias is the largest gap in this document.

r is not a constant. Etch bias depends on local pattern density (loading), so r = r(x). The theorem is unaffected — take r pointwise and the containments still hold — but the checks must use the local value, which means the density computation feeds the DRC check rather than sitting beside it.

Line-end pullback and corner rounding are systematic and directional, not captured by an isotropic ball. They are why enclosure rules exist, and a faithful model needs a structuring element that is not a ball. The theorem generalises to any convex structuring element without change; the checks get more expensive.

What it buys

Composed with 02:

LVS(D) ≅ intended    ∧    (H1) ∧ (H2) on D    ∧    E7 ⊨ (H3)
  ⟹   LVS(A) ≅ intended

That is the soundness of running LVS on drawn geometry — the inference the whole flow makes silently, now with its hypotheses named and two of the three mechanically checkable.

First experiments

• Implement (H1) and (H2) on data/pdk/inv_1.gds with a plausible r. One cell, small, and it exercises the whole pipeline: flatten, derive, erode, component-test.
• Then a row of abutted cells, to exercise the merging lemma (L1/00 O1) — recall inv_1's nwell and implants overhang the cell boundary by design, so a row's colouring is not the disjoint union of its cells'.
• Check whether SKY130's published notch/neck rules are strong enough to give (H1), or only min-width. If only min-width, (H1) has a gap in the deck itself — which would be a real finding.

Effort

The most tractable substantial result in L1: months, not years, and it needs no analysis. If one piece of the layer is formalised first, this is it.

Reading

Serra, Image Analysis and Mathematical Morphology, for the Minkowski calculus. Grisvard for what corner geometry does to the regularity that route (ii) would need.

L1/02 — Extraction and LVS

Background

A layout is polygons; a netlist is transistors and wires. Extraction is the map between them — the recognition procedure that reads a circuit back out of geometry — and its key fact is a beautiful economy of the CMOS process: a transistor is not drawn; it happens. Wherever a polysilicon shape crosses an active (diffusion) region, the crossing is a MOSFET: the poly strip over the crossing is the gate, insulated from the silicon by the thin oxide grown between them; the two pieces of active region on either side are the source and drain; and the surrounding well determines whether it is the N-type or P-type flavour. Even the transistor's electrical parameters are geometric readings — channel length L is the width of the poly strip, channel width W the extent of the active region it crosses. Wires, likewise, are just the connected clumps of metal-and-via material. So extraction is: intersect two layers to find the devices, compute 3D connected components to find the nets, record which touches which.

LVS — "layout versus schematic" — is the industrial check built on extraction: extract the circuit from the drawn polygons and compare it, as a graph, against the intended netlist. The comparison is graph isomorphism, which is notoriously hard in general and easy here for a concrete reason the chapter explains: the graph's nodes are richly labelled (device types, W/L values, port names), and the labels shatter the graph into tiny equivalence classes before any search begins. A clean LVS run is the flow's certificate that what was drawn is the circuit that was meant — which, chained with 01's sandwich theorem ("what is printed is topologically what was drawn"), yields the layer's full conclusion: what is printed is the circuit that was meant.

This chapter also owns a piece of honesty about 01: writing the composition revealed that the sandwich theorem as stated covers nets but not devices — a printed distortion could in principle sever a transistor or detach a terminal without violating any net-level hypothesis — so the device-level analogues (D1)–(D3) are added here, and the enclosure/extension design rules find their formal role as exactly those hypotheses.

Statement

The layout implements the intended netlist: Ext(M(A)) ≅ N_intended, an isomorphism of labelled graphs.

Place and route, and the certificate that replaces monolithic LVS

The statement above is LVS as an independent oracle: throw away how the layout was made, read the circuit back out of the polygons, and compare. That is the right picture when the layout is an inherited artifact of unknown provenance. Here it is not — the layout is generated from the netlist by a program this repository runs — and that changes the cheapest sound architecture. For the stages of the generator that are deterministic we validate the program once; for the stages that search we extract a certificate from the check the search already performs on the configuration it accepts. Re-deriving the whole circuit from silicon to compare against the netlist is redundant work when the netlist is the generator's own input.

What place and route are. The netlist is a graph — cells, and which pins share a net — with no geometry. Two stages give it geometry.

Placement assigns every cell instance a location and orientation in the standard-cell rows: the netlist's 203,027 instances become 203,027 COMPONENTS in the DEF, each stamped with (x, y, orient). It changes nothing logical — same instances, same nets, same incidence — placement only decorates the graph with coordinates. It is a search (minimise wirelength and congestion, meet timing) but a connectivity-preserving one.

Routing assigns every net a set of metal wires and vias that physically join its pins: the netlist's nets become 67,449 NETS in the DEF, each carrying geometry. This is where connectivity is genuinely decided — the router chooses which metal, on which layer, through which vias, realises the net — and its acceptance criterion is exactly two properties: every net's pins connected (no opens), no two nets' metal touching (no shorts).

A single net makes it concrete. In the routed DEF:

- _000000_ ( _111026_ D ) ( _053306_ X ) + USE SIGNAL
  + ROUTED met1 ( 2169590 1965370 ) ( 2174190 * )
  NEW li1 ( 2174190 1965370 ) L1M1_PR_MR
  NEW li1 ( 2169590 1965370 ) L1M1_PR_MR ;

The netlist says only "net _000000_ joins the output pin X of cell _053306_ to the input pin D of cell _111026_" — an edge, no geometry. Placement put _053306_ near (2.1696, 1.9654) mm and _111026_ about 4.6 µm to its right. Routing then chose the physical wire: a li1→met1 via at each pin (L1M1_PR_MR), and a met1 segment from x = 2.16959 to x = 2.17419 mm at y = 1.96537 mm joining them. That three-shape path is the connection. The NETS section is 67,449 such witnesses (coordinates are integer nanometres).

The decomposition. Read this way, RTL → GDS is a pipeline of stages, each with its own certificate:

Monolithic LVS — re-extract the whole 362 MB GDS and isomorphism-check it — is then unnecessary, and the extraction machinery of this chapter narrows to where it is still load-bearing: the finite cell library (each master's polygons ⊨ its CDL, amortised once — the extraction theory below), and the validation of the streamout program (which assembles the GDS deterministically from the DEF and the placed masters). The only genuinely decided connectivity in the whole flow is the routing, and the router already computed its witness and checked it — the flow runs checker-disconnectedpins (no opens) and checker-trdrc (no shorts; ChipTop.drc is empty). Passing those is the connectivity certificate; the L1 obligation becomes to re-verify that witness with a small independent checker rather than to re-derive the circuit from silicon.

This is the same search-vs-certificate split L2/04 makes for SAT — the tool stays an untrusted heuristic search; trust lives in a small checker of the witness it emits — pushed down to place and route. The extraction map that follows is now scoped to the two places it is genuinely needed, not to the chip.

Measured: the routing witness re-verified

tools/routecheck.py reads the routed DEF (ChipTop.def: COMPONENTS 203,027 placed, NETS 67,449 routed) and re-derives both acceptance properties from the routing geometry alone; check-l1 carries it as routing-witness.

No-shorts. Over all 559,285 wire segments, zero pairs of distinct nets have intersecting centerlines — a sound short-detector (crossing centerlines are a guaranteed short, independent of wire width), run by a sweep-line across each layer. This re-verifies trdrc independently of the router.

No-opens. Each net's segments and vias are unioned into connected components (endpoints, via layer-crossings, T-junctions where a via lands mid-segment, and segment crossings). All 41,287 two-pin nets self-connect — and for a two-pin net the routing is the entire connection, so this is the complete no-opens check for the 61% of nets that are two-pin. The 11 unrouted nets are exactly the 11 one-pin nets (nothing to route). The residual 3,762 multi-piece nets are all large-fanout nets whose routing additionally connects through the pin metal shapes — visible only with the cell pin geometry (LEF + placement), which is the extraction half of this chapter, not an open: the router's own disconnectedpins already certified none. Closing them is the cell-master obligation below, not a defect.

So the connectivity content of LVS is obtained here as a witness-check of the router's output — no re-extraction of silicon — with the residual precisely delimiting where the cell-library extraction is still needed.

The extraction map

Given a material distribution M (00):

Devices. Connected components of poly ∩ active. Each is one MOSFET: the component is the gate, the two active regions it separates are source and drain, the surrounding well fixes the type. This is the sense in which a transistor is the intersection of two rectangles — visible directly in inv_1, where poly (0.430 µm wide) crosses diff (0.670 × 2.250 µm).

Parameters. L = the poly dimension across the channel, W = the active dimension along it. Both are read off the geometry, which is why the geometry family propagates into device parameters and hence into E1's enclosure. (On FinFET these quantise to fin counts — a strictly easier map, since the parameter is an integer.)

Nets. Connected components of Cond(M) — 3D, through vias.

Incidence. Which device terminals meet which nets.

Ext(M) is the resulting labelled bipartite graph.

Theorem

Under 01's hypotheses (H1)–(H3), plus a device-level analogue (D1)–(D3) below:

Ext(M(A)) ≅ Ext(M(D))    for every A in the sandwich

so checking Ext(M(D)) ≅ N_intended on the drawn layout settles the fabricated one.

That composition is the soundness of LVS as actually practised, and it is the point of having 01 at all.

A gap in 01, found by writing this

01's stated conclusion includes "ν preserves incidence with device terminals", but the proof as given does not deliver it. The proof handles nets — components of Cond — and says nothing about devices, which are components of poly ∩ active and perturb under their own sandwich.

What is needed is a device-level analogue:

• (D1) (poly ∩ active) ⊖ B_r has the same number of components as poly ∩ active, each nonempty and connected — i.e. no device is severed or split.
• (D2) distinct devices stay separated: dist between components exceeds the summed radii plus overlay. Note this is a different rule from net spacing — it is poly-over-active spacing, and it is why gate-to-gate and poly-extension rules exist.
• (D3) incidence is stable: a terminal that meets net N in D meets ν(N) in A. This does not follow from (D1)+(D2); it needs the source/drain active region to remain attached to its net under perturbation, which is what enclosure and extension rules supply.

(D3) is the interesting one: it is precisely where line-end pullback bites, since a poly line end that retracts can expose channel, and a contact that pulls back can detach a terminal. So the enclosure rules flagged in 01 as "systematic and directional" are the hypotheses of (D3), not of the net-level theorem.

Action: 01's theorem statement should be weakened to nets only, with (D1)–(D3) added here. Left as-is in 01 with a pointer, so the gap is visible rather than silently patched.

Why the isomorphism check is easy

Graph isomorphism is hard in general and trivial here, for a specific reason: label diversity. Devices carry (type, W, L); nets carry names when they survive synthesis, and port nets carry them always. Refinement by labels partitions the graph into tiny cells before any search begins. Production LVS tools exploit exactly this and scale to hundreds of millions of devices.

So the difficulty is not the isomorphism. It is that Ext must be well-defined.

The real obligations

E1 (well-definedness). Ext(M) picks out finitely many devices and nets, with unambiguous terminal assignment. Non-obvious cases that must be decided rather than inherited from tool behaviour:

• a poly shape crossing active twice ⟹ two devices sharing a gate net;
• poly over field oxide (no active beneath) ⟹ no device — this is why npc and field-poly layers exist;
• abutted diffusion: two devices sharing a source/drain region with no contact between, which is a normal and space-saving idiom, not an error;
• a device whose "two sides" are actually one connected active region (a poly ring) — must be excluded or given a convention.

E2 (parameter tolerance). Real LVS compares W/L up to a tolerance, so the statement is isomorphism up to parameter windows — and the windows must contain the whole geometry family, linking directly to 01's r.

E3 (computability). All predicates are polygon boolean operations plus connected components: near-linear with a scanline.

First experiments

The generator decomposition reorders these. The chip-level connectivity certificate is the routing witness, not a re-extraction, so the first build is a checker over the routed DEF's NETS: per net, build the segment+via adjacency graph, confirm it is one connected component touching exactly the net's pins (re-verifying checker-disconnectedpins), and confirm no two nets' geometry abut (re-verifying checker-trdrc), cross-checked against the netlist's net membership. Then the two lighter obligations: the placement connectivity-preservation invariant (the DEF's instances and nets are identical to the synthesis netlist — a diff; note COMPONENTS 203027 already equals the post-route netlist's cell count), and the streamout validation (GDS = f(DEF, masters)).

The extraction theory then applies only to the library, where it is cheap and finite:

• Extract inv_1 from its shipped GDS against its CDL. Two devices expected; check W, L against the measured geometry (poly 0.430 wide over diff 0.670 × 2.250). This is the cell-master half of the decomposition, and it composes with L0/06's switch-level certificate on the same 437 cells.
• Enumerate which of E1's edge cases occur in the SKY130 HD library. If none do, well-definedness shrinks to a short list of excluded patterns.
• Attempt (D1)–(D3) on the same cell to size the device-level sandwich.

Effort

Small relative to the rest of L1, and smaller than the monolithic framing suggested: the chip-level check is a witness-verifier over 67,449 routed nets (near-linear, no isomorphism search), and the extraction algorithms run only on the finite library. The cost is in E1's conventions and the (D1)–(D3) gap above, neither deep, both of which must be decided rather than discovered.

L1/03 — The timed model

Background

The Mealy-machine picture of L2 — evaluate the logic, tick, update all flops at once — is a fiction about time. Physically, a gate's output does not change when its input changes; it changes afterward, by a delay that depends on how strongly the gate can drive its output wire, how much wire and how many listening inputs hang on it (the load), and how sharp the incoming transition was (the slew — the transition's rise time; a sluggish input edge makes the gate respond more sluggishly still, which is why slew must be tracked and propagated just like the values themselves). Signals racing through different paths of the logic arrive at different moments, and mid-race the wires hold a churn of transient values with no logical meaning.

The synchronous discipline is the design style that tames this — it is the foundational idea of digital design. Storage elements (flops) capture their inputs only at the clock edge; between edges, the combinational churn is deliberately ignored, given a full clock period to play out and settle. Correctness then rests on one local requirement per flop, in two halves. Setup: the flop's data input must have reached its final, settled value some margin before the clock edge — so every path from the previous flops must be fast enough to finish within the period. Hold: the input must then stay unchanged for a margin after the edge — so no path may be too fast, delivering the next cycle's new value while the flop is still capturing the old one. A flop whose input moves inside this forbidden window around the edge may capture garbage — including the genuinely strange failure called metastability, treated properly in 11; for now the model simply declares such a flop's output unconstrained. If every flop's window is respected at every edge, the settled values are exactly what the Boolean semantics computes, and the fiction becomes a theorem — that implication is this layer's bridge theorem (07), and the present chapter builds the model it is stated over.

One modelling decision needs flagging because everything downstream inherits it: delays in this model are intervals, not numbers. A physical gate's delay varies with manufacturing luck, voltage, and temperature; no single number is true of it. So each delay is a certified range [d_min, d_max], and every theorem quantifies over all behaviours consistent with the ranges — the same universally-quantified, worst-case style ("possibilistic," in contrast to probabilistic) used at every layer below. A theorem in this style is immune to where in its range each delay actually falls; probability enters only later, and only through the explicitly named escape hatches.

Statement

Fix the object the bridge theorem quantifies over: what "the physical circuit" means at L1's altitude. Everything in this layer is a statement about this model; its adequacy is not L1's problem — it is the conclusion of L0/07–05 and L0/09, delivered as Contracts(N).

The model

A network of components with typed terminals, driven by a clock arrival function.

Combinational cells. Each instance computes its Boolean shadow f under a bounded-delay rule: if the inputs are stable (in valid regimes) from time t, the output is stable at f(inputs) from some t' ∈ t + [d_min, d_max], where [d_min, d_max] is the cell's contract arc evaluated at the actual (input slew, output load) — an interval-valued function with an explicit domain, not a constant. Outside the domain the contract says nothing (this is where F2 bites). Output slew is likewise an interval function, because it is the next stage's input.

Wires. Each net delays and degrades: an RC enclosure from L0/09 gives interval wire delay and slew degradation per (driver, receiver) pair.

Flops. The window rule: if the data input is stable throughout [t_edge − t_su, t_edge + t_h], the output becomes that value within [t_cq_min, t_cq_max] after the edge. Otherwise the output is unconstrained — an arbitrary signal for an arbitrary time. This nondeterministic escape hatch is deliberate: it is metastability's slot in the model. Probability enters nowhere in the model itself; it enters only when 11 bounds how often the unconstrained case arises (P1).

Clock. A realised edge sequence (t_n) — the edges as they actually occur, not n·T_nom — with an arrival function arr_n : Flop → interval per edge covering tree skew. All hypotheses are per-interval: T_n = t_{n+1} − t_n ≥ T_min, plus pulse-width bounds. This coordinate choice is load-bearing: the oscillator's phase random-walks unboundedly (X5's diffusion — Var[t_n] ∝ n), but its increments are stationary with tiny variance, so event-indexed semantics with per-interval hypotheses quotients the divergent mode out entirely. Absolute time exists only at L5's interface claims, each carrying its own accuracy term. Supplied by 10; consumed by everything.

Semantics. A run assigns each net a signal (a function from time to regime-classified values) consistent with all component rules. The model is possibilistic: every downstream theorem quantifies over all runs, which is what makes interval delays sound and is the same universal-quantification move L0/00 made over field solutions.

The value lattice: 0, 1, X

Between L1/06's physical regimes and Mealy(N)'s Booleans sits a three-valued logical layer, and naming it resolves several loose ends at once. X is the untracked value: in abstract-interpretation terms γ(X) = the entire safe region of regime space, with γ(0), γ(1) the definite subregions. X covers settled-but-unpredicted values (a flop that violated its window and resolved cleanly to some rail), mid-swing transients, genuine saddle metastability, and unpowered — reserve the word "metastable" for the saddle phenomenon specifically; X is epistemic, not physical.

Three properties carry the weight:

• X is drive-recoverable. A controlling definite input forces a definite output (AND(0,X)=0); a flop capturing a definite value exits X. This is what distinguishes untracked from broken, and it is why reset works: power-up is all-X, and L3's initialisation obligation is precisely an X-elimination proof — the reset sequence, run in ternary semantics, reaches definiteness on every bit the invariant reads. Checkable by ternary symbolic simulation.
• Reading X is demonic beyond "some fixed unknown Boolean." During an unresolved window the same mid-rail wire can be read 0 by one receiver and 1 by another (thresholds differ), so the fresh-Boolean-variable model is unsound (it proves x∧¬x=0); Kleene ternary is sound because X∧¬X=X. The timed model is consistent with this for free: the escape hatch is at waveform level — one voltage, disagreement in the readers.
• Z is deleted, not modelled. Classical HDL logic is four-valued; W1/W2 (one driver per net, no floating reads — measured clean) are exactly the licence to drop the undriven value and work ternary. The unpowered case inside γ(X) matters less here than on multi-domain chips — this design has one core power domain (L5/04) — but it remains load-bearing at the pad ring, where core and IO rails differ.

This layer also gives hypothesis violations their honest meaning: an overclocked core stays physically healthy — combinational wires are ordinary late transients — but mass window violations flood the captured state with X. Mealy(N) over {0,1} stops describing the chip; the ternary machine over {0,1,X} still soundly does; the envelope still holds; recovery (restore the clock, reset, re-drive definiteness) remains provable. L5's operating-conditions clause should define "unspecified" as exactly this: envelope-bounded demonic nondeterminism — far weaker than C-style undefined behaviour.

Why this level exists at all

One could state the bridge theorem directly over Contracts(N)'s dynamical semantics. The bounded-delay model is the right intermediate because it is exactly what STA computes over — the theorem "STA pass ⟹ closure hypothesis" (08) is only crisp if the model's delay vocabulary and STA's coincide. The model is the standard one from the asynchronous-circuits literature (bounded-delay), specialised with contract-valued rather than constant delays.

Obligations

1. Adequacy is inherited, and the seam must be stated: every run of L0/08's contract-network semantics projects to a run of this model. This is a lemma against L0, not an axiom — but it must be written, because the two models' notions of "stable" (regime membership vs. voltage band) must be aligned once.
2. Well-formedness inputs: combinational acyclicity and one-driver-per-net (L2's W1/W3, to be measured on the hardened netlist).
3. The domain conditions (max_transition, max_capacitance) are part of the model: a run that exits a contract's domain satisfies the model vacuously, so the theorems above it say nothing. Cf. F2.

First experiments

• Write the model formally (signals, component rules, runs) for a three-cell circuit and check the flop escape hatch composes correctly — an unconstrained output must be absorbable by a downstream window hypothesis, not contagious by fiat.
• Prove the projection lemma (obligation 1) for a single inverter against L1/06's regime semantics.

Effort

Small — weeks of definition work. It is scaffolding, but every other file in L1 types against it.

L1/04 — SDC exceptions, and constraint completeness

Background

STA's great virtue — it checks every path — is also a problem, because some paths should not be checked. A signal crossing from an external pin with no timing relationship to the internal clock can never satisfy a setup deadline stated against that clock; a configuration wire written once at boot will never transition during operation; a path through logic that no reachable input combination can actually activate imposes a phantom constraint. Left in place, such paths either fail the analysis spuriously or force the clock slower to accommodate journeys that never happen. The industry's mechanism for handling them is the SDC file (Synopsys Design Constraints — the de facto standard format): alongside defining the clocks, it lists timing exceptions, of which the important kinds are set_false_path ("do not check this path — I assert it doesn't matter"), set_case_analysis ("analyse with this pin frozen at this constant — we are in the mode where it is"), and set_multicycle_path ("this path is allowed N clock periods rather than one").

Read those glosses again with a verifier's eye: every exception is a human assertion that removing a check is sound — and no tool anywhere validates any of them. The STA engine obeys the SDC as commanded. An exception wrongly omitted merely costs frequency; an exception wrongly added deletes a real check, and the resulting chip carries a timing violation that no analysis ever saw. Exception inventories are one of the largest unaudited trust surfaces in industrial flows — hand-maintained chip-level SDCs routinely carry hundreds of assertions in a Tcl program whose evaluation is itself a task.

This design's constraint file makes the opposite trade, and the audit inverts with it. The flow generates the SDC, and what it generates is minimal: one declared clock (the external core clock, with an uncertainty margin), default driving-cell and load models, and zero exceptions — no false paths, no case analysis, no multicycle paths. There is nothing over-asserted to audit. The trust surface moves to what is missing: the design has more clock domains than the SDC declares — the JTAG port clocks the debug transport logic from its own pin, and the serial TileLink bridge clocks its pad-side half from the link clock — and a path in an undeclared domain is not excepted, it is simply unanalysed. Unconstrained-is-unchecked is more dangerous than excepted-with-a-claim, because no assertion exists to audit.

Statement

Every path STA skips carries a claim that skipping is sound — whether the skip is an explicit exception or a silent gap in the constraints. This file audits both directions: the (empty) exception inventory, and the completeness of the constraint set against the design's actual clock-domain structure.

The measured inventory (the generated ChipTop.mapped.sdc plus the clock fragment): 1 create_clock (clock_uncore, 50 ns, 2 ns uncertainty), 1 trivial set_clock_groups, 0 set_false_path, 0 set_case_analysis, 0 set_multicycle_path.

Step zero: what the constraints do not say

The audit's first deliverable is the diff between the declared clock set and the netlist's clock-domain census (10's machinery):

The gaps are not necessarily unsound — the crossings in question land in synchroniser structures (11's inventory), and the domains are low-speed — but "necessarily" is exactly what an audit refuses to assume. Each row must end in one of: a declared clock plus analysed crossings; a justified exception with its discharge; or a recorded finding that the flow's signoff does not cover the domain.

The claim classes, kept ready

The four-way classification the audit framework carries (from designs whose files do have exceptions), because rows will appear here as the constraint set is completed:

Logically false carries one classical trap worth keeping in view: the correct criterion is about transitions, not values. Static (one-vector) sensitisation is both unsound and incomplete for delay — the honest query is "no input/state pair propagates a transition along the path" (the false-path/viability literature, McGeer–Brayton). The safe direction for justifying an exclusion is the two-vector unsatisfiability, which is a well-defined SAT obligation on the netlist plus a reachability assumption on the state.

Asynchronous is where the undeclared domains will land when the set is completed: declaring a crossing false does not make the interface safe; the actual claim is that the receiving endpoint treats the data as unconstrained, i.e. a synchroniser stands behind it — a structural netlist predicate (two-flop chain, no combinational fanout from the first flop, single-domain clocking) plus P1's residue — 11's machinery, not SAT.

Multicycle, for the record, asserts two things (destination not enabled on intervening edges; source held stable throughout) plus a hold-side adjustment that defaults wrong. This design declares none — a genuine simplification, noted so its absence is recognised as load-bearing.

The work plan

1. The clock-domain census against the netlist (10); the domain/SDC diff table pinned by the layer's checker.
2. Per gap: complete the constraint (declare the clock, constrain the crossing) or record the finding — with the flow re-run under the completed set, since new constraints can surface new violations.
3. The synchroniser predicate over the crossing endpoints (11), replacing assumption with structure.
4. The reset-recovery constraint question settled explicitly.

Obligations

1. A formal semantics for the flat constraint set (what a declared clock, an uncertainty, and any future exception mean to 08's plumbing).
2. The completeness theorem shape: every sequential element's clock pin traces to a declared clock, or its absence is a named finding.
3. The two-vector sensitisation query, stated against Mealy(N), held ready for the first real exception.
4. The synchroniser predicate, shared with 11.

Effort

Weeks, needing only the flow's own artifacts. The audit is smaller than a hand-written chip's — the generated file has nothing to elaborate and nothing over-asserted — and the completeness half is the part with teeth.

L1/05 — Crosstalk and the power grid

Node: this file is the object — the two interference budgets (crosstalk and power-grid droop) absorbed at L1. The combinatorial theorem that discharges the droop budget is the edge, 13.

Background

Two wires running side by side for any distance form a capacitor: charge moved on one induces charge movement on the other, through nothing but proximity. On a chip whose routing layers are packed with parallel wires at minimum spacing, this coupling capacitance makes every net a potential radio: when an aggressor net switches, a neighbouring victim feels it. The interference — crosstalk — takes two forms, one for each state the victim can be in. If the victim is switching at the same moment, the aggressor's motion effectively changes how much capacitance the victim must charge (the "Miller factor" of the analysis below: an opposing transition can as much as double the effective coupling, an assisting one cancel it), which shifts the victim's delay — a timing effect. If the victim is sitting still, the aggressor's edge injects a glitch — a transient voltage bump that the victim's driver must fight down before any listening gate mistakes it for a real transition.

The defence against glitches is the digital abstraction's own noise margin: a gate does not respond to small wiggles — its input can move some hundreds of millivolts off the rail before the output does anything — so a glitch provably smaller than the margin is nothing, absorbed as if it never happened. (This restoration-by-indifference is the voltage-domain sibling of the restoration patterns met elsewhere in the tower.) The proof obligation is then a per-net inequality — worst-case sum of all aggressors' injections stays under the margin — and, at this design's generous 130 nm voltages, the inequality can be made to hold by routing rules alone: bounded parallel run lengths, spacing, or a grounded shield wire between critical nets. Geometry, checked once, and no trace of the phenomenon survives to any higher layer.

The chapter's second subject is the power grid. Supply voltage is not a given constant: every switching gate draws a current spike through a resistive metal mesh, and the resulting sags (IR droop) locally slow every gate — a potential back-door coupling between activity and timing that could entangle everything with everything. The design's counterweight is the decap army (the 125k+ decoupling capacitors of L2/02's census — local charge reservoirs that supply the spikes so the grid doesn't have to), and the verification strategy is to compress the entire phenomenon into a single impedance bound: the grid, decaps included, presents a low enough impedance across the relevant frequency band that no cell's supply leaves a stated window. Inside that window, supply variation is already covered by the voltage tier of 09's corners; beyond it lives the small residual probability P_droop, the third and last summand of the project's ε.

Statement

The two analog phenomena that could force their way into the discrete interface — coupling between nets, and supply variation — and the arguments that keep them out. Both are absorbed at this layer: nothing above L1 sees either, and preserving that is a design constraint, not an accident.

Crosstalk: two effects, two absorptions

Coupling capacitance C_x between a victim and an aggressor (L1's coupling graph) acts twice:

Delay shift (victim switching). The classical model: effective coupling ranges over {0, 1, 2}×C_x by relative transition direction — the coupling Miller factor, named for the feedback-capacitance multiplication of Miller (1919). Absorb it by widening the victim's load interval — C_eff ∈ [C_g, C_g + 2C_x] for setup, [C_g, ...] floor for hold — and the coupling graph disappears into the per-net RC interval. Honesty note: the 2× ceiling is a fact about equal-slew ramp models, not a theorem — Chen, Kirkpatrick & Keutzer showed the factor needed for worst-case delay exceeds the naive range with mismatched slews. The rigorous version derives the factor from the contract network (slew-dependent), which is exactly the kind of lemma L0/08's machinery exists for — assume the classical bound only until then, and say so.

Glitch (victim quiet). An aggressor transition injects charge; the victim's driver fights it. The check: worst-case over all aggressors switching together,

Σ_aggressors  (C_x / C_total) · ΔV · f(driver strength, slews)   <   NM

with NM from L1/06. If this passes per net, nothing is exported at all — a glitch that never leaves the noise margin never becomes a logical event.

The discharge is geometric. Both absorptions reduce to routing-rule checks: maximum parallel run length at minimum spacing, spacing or shielding on the exceptions. Structurally identical to tap coverage — a layout predicate, checked once (L1/G-machinery), never seen again. Feasible at 130 nm/1.8 V precisely because the margins are wide; at 7 nm the worst-case sum fails routinely and industry prunes by timing-window intersection instead — which still preserves the layering (no functional information flows downward), but couples the noise check to 08's arrival windows. Levers if a net fails, best first: shielding (topological, exactly zero — L0/10's Step 1), spacing, run-length limits, slower edges.

The red line: treat any net needing a functional coupling constraint as a layout bug. "These two nets never switch together because the FSM forbids it" entangles the noise argument with L3's invariant — the one dependency direction this project's layering exists to prevent. Fix the layout instead; the option always exists at this node.

The power grid: enters exactly once

The grid could contaminate everything — every delay depends on V. It is kept to a single entry point:

The equipotential bound. The grid's impedance to the rails, over the frequency band set by the design's edge rates, is below the threshold making supply excursions at any cell ≤ ΔV_grid. Established by the ~225k decaps (the impedance bound is why they exist); discharged once as a frequency-domain claim.

Downstream of this single bound: (i) the voltage tier of 09's corners covers V ± ΔV_grid — supply variation becomes corner content, not a new mechanism; (ii) L0/10's screening theorem gets its Dirichlet hypothesis — the grid is a shield only if it is an equipotential, so the decaps are doing double duty (delay stability and shield quality); (iii) the residual — droop beyond the bound under worst-case simultaneous switching — is P_droop in the overview's ε, a P6-class environment/design bound.

Slower edges relax the band over which the impedance bound must hold and shrink both crosstalk effects — one more independent way a conservatively-clocked design is cheaper to verify, and by now the third such coincidence (cf. the slew-limit domain conditions, the serial link's relaxed link-clock budget).

The equipotential bound above states what the grid must satisfy; how it becomes checkable without a full-chip network solve — the M-matrix monotonicity and lattice Green's-function collapses that turn the droop residual into a sound combinatorial verdict — is the edge that carries this budget, 13.

Obligations

1. The Miller-factor lemma from the contract network (or the explicit assumption, flagged, until then).
2. The glitch check as a per-net computation over L1's coupling graph + L0's NM — plus the routing-rule predicate that makes it pass by construction (L1/G5-adjacent).
3. The grid impedance bound: state it, and identify what discharges it (decap census + package model — partially X4/P6 territory). The combinatorial droop certificate and the di/dt piece that discharge this bound are the edge's obligations, 13.

First experiments

• Extract the coupling graph for the worst few nets from the flow's SPEF and run the glitch sum against SKY130's noise margins. If the worst net passes with margin, the whole absorption strategy is confirmed cheap for this design.
• Census the parallel-run lengths in the routed DEF against a candidate rule — is the geometric discharge already true of the flow's layout, or does it need the timing-window fallback anywhere?

Effort

Months, mostly tooling over DEF/extraction data; the two lemmas (Miller, equipotential) are the only theory, and both lean on machinery other files already need.

L1/06 — The digital abstraction as a regime decomposition

Background

This is the chapter where "the voltage is a 0" gets its definition, and the mathematics that hosts the definition is dynamical systems — the study of states evolving under fixed laws — so its basic furniture is worth setting out. The circuit's state (all node voltages together) is a point in a high-dimensional state space, moving along a trajectory determined by the device equations and the inputs. A fixed point is a state that maps to itself — the circuit at rest; an attracting fixed point pulls nearby trajectories in, so small displacements die out. An invariant set is a region trajectories cannot leave; robust invariance means they cannot leave even when the dynamics are perturbed by bounded disturbances — noise, supply wobble, coupling. The digital abstraction, properly stated, is a claim of exactly this shape: the state space decomposes into named regimes ("this node denotes 0," "this node is mid-transition"), the denoting regimes are robustly invariant and attracting, and transitions between them complete in bounded time. The chapter's (I)/(P)/(A) triple is that claim made precise.

The textbook version of this story — every electronics course tells it — is the static noise-margin argument: plot a gate's output voltage against a slowly-swept input (the DC transfer curve), observe gain > 1 in the middle, conclude the rails are attracting and there is a margin of input error each stage absorbs. True, and insufficient: it is a statement about equilibria, and a computing circuit is almost never at equilibrium. Upgrading "the steady states are attracting" to "trajectories with bounded disturbances stay in the regime tube and progress through it on schedule" is precisely the gap between the textbook and a theorem, and it is the real content here.

Fortunately, robust invariance is a developed engineering discipline with certificate-shaped tools. A Lyapunov function is the classic one: a scalar "energy-like" function that provably decreases along every trajectory, so the system must descend toward its minimum — exhibiting one is a proof of convergence, no trajectory enumeration needed. A barrier certificate is its safety sibling: a function separating the good region from the bad whose gradient condition shows no trajectory can cross the dividing surface. Both are found in practice by sum-of-squares programming — a method that searches for polynomial certificates by convex optimisation, writing "this polynomial is nonnegative" as "it is a sum of squares," a form both machine-findable and, crucially for this project, machine-checkable after the fact. The search is numerical and untrusted; the found certificate is algebra a proof assistant can verify — the same search-versus-certificate split the SAT world uses, transplanted to continuous dynamics.

One preview of a profound consequence. The progress claim (P) — transitions complete in bounded time — provably cannot be made unconditional: a classical theorem (Marino, 1981) shows any bistable device with continuous dynamics can be driven to sit arbitrarily long between its states. That failure mode is metastability, already met from the consumer's side in L1/11; here it appears as it really is — not an engineering blemish but a topological necessity, the one permanently unclosable hole in the digital abstraction, and the reason the axiom ledger carries P1 forever.

Statement

The physical state is a field configuration evolving in time — potentials and carrier densities over the domain, driven by environmental inputs. The digital abstraction is a decomposition of that state space into regimes, plus three claims:

regimes:   U           unpowered / at rest
           Z₀ⁿ, Z₁ⁿ    node n denotes 0 / denotes 1
           Tⁿ          node n transitioning

(I)  INVARIANCE   starting in a valid regime with bounded inputs, you stay in the
                  union of valid regimes — you never escape to "undefined"
(P)  PROGRESS     from Tⁿ you reach the appropriate Z regime within bounded time
(A)  ABSTRACTION  the induced discrete transitions are exactly the Boolean/Mealy semantics

The digital state is a tuple over nodes, so the regime structure is a product; the decomposition is a covering of an infinite-dimensional state space, not a partition of a scalar.

Tⁿ is not a single set but a family parameterised by transition time: delay and crowbar current depend on the input trajectory, not its endpoints, so "transitioning" carries its slew with it. This is why the per-component contract (07, 08) is stated on trajectory classes rather than voltage regions — a static region cannot support the composition.

Why the static story was wrong

The textbook argument — DC transfer characteristic, gain > 1 in transition, rails as attracting fixed points, V_OL < V_IL — establishes only that the steady states are attracting. It says nothing about trajectories, and a circuit spends much of its life not at a steady state.

The static picture is the equilibrium slice of (I): it characterises the invariant sets but not the invariance, and not (P) at all.

What the correct framing buys

Several things I had scattered across documents turn out to be the same object:

• Noise margin is not a static gap. It is the robustness radius of the invariant set — how large a disturbance the region tolerates while (I) still holds.
• Restoration is the contraction that makes the invariant set attracting, i.e. it is what proves (I) and (P), not a separate phenomenon.
• Metastability is exactly the failure of (P). From Tⁿ you may not reach a Z regime within bounded time; the exponential tail exp(−t/τ) is the reachability-time distribution. It is not a separate pathology bolted onto the model — it is the one place the model's progress claim has no bound. And this is a theorem, not an engineering observation: Marino (IEEE Trans. Computers 1981) proved by a connectedness/continuity argument that any bistable device with continuous dynamics admits inputs driving it to arbitrarily long settling — no clever circuit escapes it. So (P) provably cannot be made unconditional, which is the formal justification for carrying P1 as an axiom rather than filing it as an open problem.
• The setup/hold window is the condition under which (P) holds for a flop. Which is precisely why L1's bridge theorem needs it as a hypothesis.
• The switching window is where no Z regime holds — so it is unsurprising that disturbances get amplified there rather than attenuated.

The mathematics

This is a robust invariance problem for a controlled dynamical system with bounded disturbances. Standard tools apply:

• Barrier certificates for (I): find B(state) with B ≤ 0 on the initial set, B > 0 on the bad set, and Ḃ ≤ 0 on {B = 0}. Constructive and checkable, and the standard method in hybrid-systems verification (Prajna & Jadbabaie).
• Lyapunov functions for (P): a functional decreasing along trajectories toward the target regime, with a decrease rate giving the time bound.

Both are found in practice by sum-of-squares programming (Parrilo; SOSTOOLS as the front-end, an SDP solver underneath), and — importantly for this project — the checking side is already formalised: a numeric SOS certificate can be rounded to a rational identity and verified in a prover, which is exactly what Harrison's HOL Light SOS procedure and Martin-Dorel & Roux's ValidSDP (Coq) do. So the pipeline "search numerically, certify formally" exists end to end for polynomial dynamics; the work is getting an interval-valued device model into polynomial (or polynomial-envelope) form.

There is a natural candidate at the field level. The van Roosbroeck system has a free-energy functional that decreases along trajectories — this is the structure Gajewski and Gröger used to prove global existence and asymptotic behaviour for the transient system. That is exactly a Lyapunov functional, and it is the physical basis for "the circuit settles."

Caveat: the free energy decreases toward thermal equilibrium, i.e. toward the unpowered regime U. For a driven circuit the relevant statement is convergence to a boundary-driven steady state, so the working functional is a relative free energy with respect to that steady state rather than the equilibrium one. That adaptation is where I would expect the real work to be.

Environmental bounds are hypotheses, and you named the right ones

(I) and (P) are conditional on the inputs staying in range. Concretely:

So the theorem is robust invariance: invariance under all disturbance signals within these bounds. The unbounded ones (P2's particle strikes) are exactly the ones that can kick you out of the invariant set — which is the correct formal statement of why SEU is the only surviving probabilistic term.

Finite-dimensional reduction

Doing this in the infinite-dimensional field setting is PDE stability theory. Doing it on the lumped model is finite-dimensional and tractable — barrier certificates over a few state variables per cell.

L0/08 is what licenses the reduction, so the dependency is: well-posedness (00) → quasi-static reduction (01) → lumping (04) → this document in the lumped world, with (04)'s error term entering as a disturbance the invariance must be robust against. That last point is worth stating explicitly: the lumping error is not a separate approximation to be apologised for, it is a disturbance signal, and robust invariance already has the machinery to absorb it.

Handoff

L1/06 establishes that transitions complete. It does not say how fast — that is L1, which quantifies the time bound (delay), checks it against the clock period, and turns (P) into the setup/hold constraints. So:

L1/06 : (P) holds with SOME bound
L1    : the bound is ≤ T_clk − setup − skew, and the design meets it

The bridge theorem is the composition of the two.

Reading off the Boolean function

Given (I), (A) reduces to a finite check per cell: for each of the 2ⁿ input regime combinations, the output's invariant regime is f(inputs). Standard cells have few inputs, so this is exhaustive and cheap once the invariant sets exist — the work is all in (I).

Note this needs only a coarse device model: you need the regimes to be separated, not accurate currents. That materially weakens what E1 must assert.

Where the abstraction is not in force

• During switching — no Z regime holds; this is (P)'s domain and metastability's home.
• Tri-state / pass-transistor nodes — a floating node has no driver, so there is no attracting invariant set; the value is held by charge and decays. Needs separate treatment, and L2's one-driver-per-net well-formedness condition is the structural counterpart.
• Below the design point — ΔE/kT = ½C(ΔV)²/kT is not scale-invariant. At the 1.8 V design point the noise-margin barrier (ΔV ≈ 0.25 V, C ≈ 1 fF) is ~7,500 kT; near-threshold it falls to ~10³ kT. Still uncrossable, but 2,800 orders of magnitude vanish quietly. The abstraction is robust because designers keep it robust, so the noise margin must be a checked quantity, not an assumed one.

Open problems

1. State (I), (P), (A) formally for the lumped model, with the regime sets explicit. This is the honest form of "the digital abstraction", and I do not know of it being written down anywhere for real CMOS.
2. Construct barrier certificates for a standard cell from an interval-valued device model. If this works for inv_1 it plausibly works for the library.
3. Adapt the free-energy Lyapunov functional to the boundary-driven steady state. The equilibrium version is established; the driven version is what circuits need.
4. Time bounds from the Lyapunov decrease rate, and their relationship to the Liberty tables — these ought to be the same quantity derived two ways, which is a strong consistency check on L0/07.
5. Tri-state and pass-transistor cells: does the shipped configuration use any?

First experiments

• Write (I)/(P)/(A) for a single inverter in the lumped model, with explicit regime sets and disturbance bounds. Small, concrete, and it will immediately show whether the framing survives contact with a real device model.
• Attempt a barrier certificate for that inverter (SOS programming is the standard route).
• Check whether the Lyapunov time bound and the Liberty delay agree in order of magnitude.

Effort

The single-inverter (I)/(P)/(A) instance: weeks. The driven-steady-state Lyapunov adaptation (M7) is the open-ended piece.

Reading

Gajewski & Gröger on existence and asymptotics for van Roosbroeck, and the free-energy functional. Prajna & Jadbabaie on barrier certificates; Parrilo on SOS relaxations; Harrison and Martin-Dorel & Roux (ValidSDP) for prover-checked certificates. Blanchini on set invariance in control; Lohmiller & Slotine for contraction. Marino, "General theory of metastable operation" (IEEE Trans. Computers 1981) — the unavoidability theorem; Kinniment, Synchronization and Arbitration in Digital Systems, for the engineering side. Standard hybrid-systems abstraction literature for the (I)/(P)/(A) pattern — this is a well-worn shape, just not usually applied this far down.

L1/07 — The bridge theorem (M5)

Background

Every layer above this point reasons about the chip as a clocked state machine: state now, one step, state next. That picture is not physics — it is a theorem-shaped claim that industrial practice believes, acts on, and has never stated. Designers say the design "meets timing" or "closes timing" (timing closure), meaning the checking tools report that every flop's setup and hold requirements are satisfied at the intended clock period; and everyone proceeds as if closure implies the discrete abstraction is sound. The implication is almost surely true. It is also nowhere written down as mathematics — with its hypotheses enumerated, its conclusion stated over a defined model, and its edge cases forced into the open. Writing it down is this chapter, and the exercise is the book's central specimen of the pattern "a design rule is secretly a hypothesis of a theorem nobody wrote."

The proof shape is worth previewing in words because it explains why the synchronous discipline works, not just that it does. It is an induction over clock cycles, and the invariant is simply "at the start of each cycle, every flop stably holds the state the Mealy machine says it should." Given that, the settled combinational values are the right ones by the time the setup margin requires (the fast enough half); the newly-launched values of the next cycle cannot corrupt the capture (the not too fast half, hold); so the edge captures exactly the Mealy machine's next state, and the invariant is re-established — fully, every cycle. That last point is the profound one: the clock edge is a restoration point in time. Nothing carries over; timing error does not accumulate across a trillion cycles any more than voltage noise accumulates across a chain of restoring gates. The tower's recurring motif — every layer has a mechanism that resets its own error to zero — appears here in its temporal form.

The asymmetry between the two halves also deserves plain statement, because it drives real engineering behaviour. The clock period appears in the setup inequality only: a setup-slow chip can always be rescued by clocking it slower, which is why vendors can sell slower parts from an imperfect batch ("binning"). Hold contains no period at all — it is a race between two paths launched by the same edge — so a hold-violating chip is broken at every frequency, forever, in silicon. Hold bugs are the ones that kill tapeouts, and the reader will see hold appear as the sharp edge in several findings below.

Statement

Over the timed model of 03:

Let N be the hardened netlist, partitioned into clock domains with declared asynchronous boundaries (11). Suppose:

1. (domain) every cell's load and input slew lie inside its contract's domain — max_capacitance / max_transition — an F-series row until the flow's signoff closes it;
2. (closure) setup and hold hold at every flop, at every corner, with respect to the clock arrival function — certified by STA (08) — likewise an F-series row until multi-corner closure is achieved and pinned;
3. (constraints) the constraint set is complete — every domain declared, every excluded path justified (04);
4. (conditioning) no fault event (P2) and no unresolved synchroniser read (P1) occurs in [0, T].

Then every run of the timed model over [0, T] agrees with Mealy(N): at each clock edge n, every flop holds s_n, and s_{n+1} = δ(s_n, i_n).

Everything above L1 presupposes this, and nobody has written it down. It is the highest value-per-effort novel contribution in the project.

Proof sketch

Induction on clock cycles with invariant "at the start of cycle n, all flops hold s_n stably."

• Propagation. From the invariant, the combinational DAG settles: max-delay bounds along every path (hypothesis 2's setup half) give all flop inputs stable at δ(s_n, i_n)-consistent values by arr(f) − t_su for every flop f.
• No early corruption. Min-delay bounds (the hold half) give that no flop input changes before arr(f) + t_h — the new values racing through short paths cannot violate the just-captured state.
• Capture. The window rule fires deterministically at every flop; outputs become s_{n+1} within t_cq, re-establishing the invariant. ∎

Three structural remarks that carry more weight than the induction itself:

The clock edge is a restoration point in the time domain. The invariant is fully re-established every cycle, so timing error does not accumulate — the same mechanism, in time, as gate restoration in voltage. There is no drift mode: a violated constraint fails immediately and deterministically, not gradually.

Setup and hold are asymmetric, and only one is negotiable. T_clk appears in the setup inequality and is absent from the hold inequality. Setup failure is a performance property (clock slower); hold failure is unfixable at any frequency, post-silicon. Corollary: CTS is not logically neutral — hold depends on skew, and useful skew makes the clock tree an active participant in correctness (10).

Cycles are already cut. Every feedback loop passes through a flop (W3, measured: exactly one exception, excised). Cutting at flops turns the cyclic sequential graph into a DAG of combinational segments, each with one max- and one min-delay obligation — which is why STA is a graph traversal and the induction needs no fixed point.

Where the theorem's shape breaks

Each of these violates a hypothesis structurally, not numerically:

The conditioning is the theorem's honest edge

Hypothesis (4) is not a technicality: it is where ε enters the whole project (the overview's † marks). The theorem is deterministic on the event "no strike, no unresolved read"; 11 and L0/03 bound the event's complement. Stating M5 unconditionally would be false; smearing the probability through the induction would be unworkable. The conditional form is the correct interface.

Open problems

1. Write it. Bounded-delay model, window rule, per-cycle induction — a solid paper, not a decade. Its absence is a fact about nobody working at the boundary, not about difficulty. Lööw's stack is the closest prior art and stops short of this statement.
2. The multi-domain version: the theorem above is per-domain; the composition across declared boundaries is 11's.
3. Whether hypothesis (1) can be weakened from "in domain" to "in domain or provably unobservable this cycle" — domain violations on dead nets would then not falsify the hypothesis; worth stating before the first signoff report is adjudicated.

First experiments

• State and prove the single-domain theorem for a toy: two flops, three gates, interval delays. Every structural feature (both window halves, the escape hatch, slew propagation) already appears at this size.
• When the flow's signoff reports slew/cap violations, check whether the violating nets are functionally dead (open problem 3) — cheap, and it decides how each report adjudicates.

Interface (up). This theorem is the S-timing seam of the end-to-end composition (iface_L1_timing, dieBeh = timedBeh): the arrow by which every layer above L1 earns the right to reason discretely. The whole L1 board discharges its hypothesis — closure with margin at every corner — while the reduction itself is the open content here.

Effort

Months for the single-domain statement and proof; the multi-domain composition rides on 11.

L1/08 — Verified STA

Background

How does anyone check setup and hold across a design with hundreds of thousands of paths? Not by simulation — no test could exercise every path at its worst — but by static timing analysis (STA): a tool that never runs the design at all. It treats the netlist as a graph whose edges are annotated with delay ranges, and computes, for every node, the earliest and latest possible moment a signal transition can arrive there — a longest-path/shortest-path computation over a DAG, polynomial and fast. Comparing each flop's latest arrival against its setup deadline and earliest arrival against its hold requirement yields a per-flop slack (margin: how much room is left, negative meaning violated), and a design "meets timing" when no slack is negative. Because it covers all paths by construction rather than the exercised ones, STA is the industry's sign-off instrument — the analysis whose verdict is the go/no-go for fabrication.

Where do the edge delays come from? From the Liberty file, the cell library's timing characterisation: for each cell, each arc (this input to this output), the library vendor ran analog circuit simulations across a grid of operating points and tabulated the results. A delay is looked up, in a table indexed by the two context quantities that L1/03's background introduced — the input's slew and the output's load — and since the arguments rarely land exactly on grid points, the tool interpolates between samples. That one word carries this chapter's hardest problem: interpolation is an estimate, not a bound, and the measured tables are not even monotone (a slower input edge occasionally yields a smaller tabulated delay — an artifact of how "delay" is anchored to waveform midpoints; the physics behind it is 09's subject). A verified STA must replace every such convenience with something that is actually sound, and the three deviations catalogued below are where standard practice and soundness part ways.

"Verified" here means the strong sense established elsewhere in the book: not a carefully-written reimplementation, but an engine accompanied by a machine-checked theorem that if the pass reports no violation, then hypothesis (2) of the bridge theorem holds in the timed model. The algorithm is textbook; the content is the soundness statement — and, as so often in this project, the places where proving soundness forces the discovery that the standard practice being formalised quietly isn't.

Statement

If the STA algorithm, run over the contract arcs and the clock arrival function, reports no violation on any non-excepted path at any corner, then hypothesis (2) of the bridge theorem holds.

STA is a decidable, polynomial graph algorithm — longest/shortest path on a delay-annotated DAG. Verifying an implementation of it is ordinary work; the content of this file is the soundness statement connecting the algorithm to the model, and three places where standard practice is subtly unsound and the verified version must deviate.

The algorithm

Forward pass over the flop-cut DAG, per corner:

arr(n)   = max over fanin edges e of  [ arr(src e) + cell_delay_e(slew_in, load) + wire_delay_e ]
slew(n)  = slew table of the winning/merged arc          ← propagates WITH arrival

then backward required times from each flop's window (arr_clk(f) − t_su for setup at the slow corner, arr_clk(f) + t_h for hold at the fast corner), and slack = required − arrival. Hold uses min-delay arcs and the early/late clock split; CPPR credits the shared clock-path prefix once (09).

Composition is a traversal, not a sum: both table arguments are context-dependent (load from L1's extraction, slew from the upstream cell), so per-cell delays cannot be precomputed. Setup/hold constraints are themselves 2-D tables of (data slew, clock slew).

Three unsoundnesses in standard practice

The verified version is not a transcription of an industrial engine; these must be done differently.

1. Interpolation must use the enclosing box, all four corners. cell_fall is non-monotone in input slew at two grid points of the simplest cell in the library (measured — Findings). Bilinear interpolation between samples is a model choice, not a bound; the sound rule is the max/min over all four surrounding grid points, and even that is a bound only given an inter-sample variation assumption, which E2's discharge route (L0/07) must supply as a derivative bound on the table.

2. Worst-slew merging is conservative only under monotonicity. Graph-based STA propagates a single merged (worst) slew at reconvergence. "Worst slew ⟹ worst delay" is exactly the monotonicity that the measured tables violate. The sound options: propagate slew intervals, or fall back to path-based analysis on the paths where the table is non-monotone. This is M4 surfacing inside the algorithm, not just in the corner methodology.

3. Negative delays are legitimate, but causality bounds them — check it. A delay entry is the difference of two 50%-anchor labels, and at light load / slow slew the output's label can precede the input's (conduction starts at V_th, below the anchor — 09's mechanism), so d < 0 is bookkeeping, not back-propagation. But the output cannot respond before the input starts moving, so d ≥ −(t₅₀ − t_start) ≈ −O(slew) with the coefficient set by the library's trip-point conventions. An entry below that bound is a characterisation error. This is a mechanical table-validity sweep, and it matters doubly for hold: negative min-delay entries shorten short paths, so an erroneously negative entry manufactures phantom hold violations — or masks real ones if clamped to zero, which some tools do and which is exactly the kind of silent repair a verified engine must not perform.

4. Domain checking is part of the pass, not a lint. Every table lookup must assert its arguments lie inside the characterised region (max_transition, max_capacitance). Outside it the industrial tool extrapolates and the result is vacuous rather than wrong — max-slew and max-cap violations, which real runs of this flow do produce, are exactly reports that parts of the design sat outside the characterised region (the F-series tracks them). In the verified engine an out-of-domain lookup is a failed hypothesis, reported as such.

Plumbing to the exceptions

STA does not decide which paths matter; the SDC does. The soundness statement is therefore conditional: the pass certifies closure on non-excepted paths, and every excepted path must carry a justification per its class (04). The verified engine's job includes emitting the exact excluded-path set, so that (3)'s obligation is discharged against what was actually skipped rather than against what the Tcl was believed to mean.

Obligations

1. The soundness theorem above, against 03's model — the real content; the traversal itself is textbook.
2. The interpolation enclosure with the derivative-bound side condition (from L0/07).
3. Slew-interval propagation or a per-arc monotonicity certificate (with 09).
4. Re-derive the flow's timing verdict with the verified rules and compare against its own STA reports — agreement is evidence, disagreement is a finding either way.

First experiments

• Run the interpolation enclosure over the full SKY130 HD library: for every cell, arc, corner, check monotonicity in both table arguments and measure how wide the four-corner enclosure is versus bilinear. Mechanical; directly sizes how much pessimism soundness costs, and produces the M4 violation census as a by-product.
• Reproduce one path's arrival time by hand from the tables against the signoff report's value.

Effort

The engine: months (it is a few hundred lines plus the table machinery). The soundness proof: the larger half, and it depends on 03 being written first.

L1/09 — Corners and correlation (M4)

Background

No two copies of this chip are identical. Fabrication is a statistical process — dopant counts, oxide thicknesses, and etch widths all vary — so transistors on one die are a few percent faster or slower than on another, and even neighbouring transistors on the same die differ slightly. On top of manufacturing variation, delay depends on operating conditions: a gate at 1.6 V and 100 °C is markedly slower than the same gate at 1.9 V and −40 °C. A timing verdict must therefore hold not for one circuit but for a whole family of circuits, indexed by a parameter space: the process outcome, the supply voltage, the temperature — P, V, T in the trade's abbreviation.

Industry's answer to "how do you check a continuum?" is the corner: a small set of consistent worst-case parameter assignments. The library ships each cell's timing characterised at points like ss_1.60_100 — slow-NMOS/slow-PMOS process, 1.60 V, 100 °C — and its mirror ff (fast/fast) at high voltage and low temperature; run STA at every corner, and if all pass, declare the whole box covered. Note the structure of the move: rather than treating every gate's delay as independently uncertain (which double-counts the shared physics and compounds into hopeless pessimism — a die where alternate gates came out fast and slow is not a thing fabrication produces), corners evaluate correlated extremes, all gates slow together or fast together. Setup is checked where everything is slow, hold where everything is fast.

The logical leap in this practice is the reason this chapter exists. Checking the box's vertices covers its interior only if delay responds monotonically to each parameter — a function that peaked somewhere in the middle of the voltage range would evade every corner. Monotonicity is physically plausible, universally assumed, and never stated as the hypothesis it is; this book files it as open mathematics (M4). And the plot thickens on contact with data: the measured library tables are not monotone (the census below found genuine sign changes), for a reason that turns out to be an artifact of how "delay" is defined rather than of the physics — the resolution, which involves distinguishing the monotone waveform-level truth from its non-monotone tabulated shadow, is the heart of the chapter.

The remaining vocabulary of the trade, in one breath: OCV ("on-chip variation") is the per-cell random component left after die-wide correlation is accounted for — it accumulates down a path as √n, not n, because independent random errors partially cancel; a derate is the industry's flat percentage margin approximating that effect; and CPPR ("common path pessimism removal") is the correction that stops a shared clock-distribution prefix from being counted as slow for the launching flop and simultaneously fast for the capturing flop — the same physical wire cannot be both.

Statement

Delays are not numbers but functions of process, voltage and temperature parameters. The question this file owns: when is it sound to check finitely many parameter assignments? Corner methodology — the entire industry's answer — assumes yes; the assumption is M4, and production data already violates its usual justification.

The problem naive intervals have

Propagating per-cell delay intervals independently is sound and useless: the same physical uncertainty is counted independently at every use site, admitting assignments no die realises — this cell slow, its neighbour fast, the first slow again. The pessimism compounds along paths and closure becomes impossible at any frequency.

Corners fix this by evaluating consistent assignments: all cells slow together (ss), one voltage, one temperature. The library ships 17 of them. But finitely many consistent points bound the continuum only under a monotonicity premise:

(M4) If the response (path delay, slack) is monotone in each parameter over the box, its extremes over the box are attained at vertices — so checking the corners is checking the box.

Status: the premise is not free

cell_fall(inv_1) is non-monotone in input slew at two grid points (measured). Slew is not itself a corner parameter, but it is the composition variable through which corner parameters act on downstream delays — so the clean argument "everything is monotone in P/V/T, therefore corners suffice" has a hole in its transfer step.

Where the non-monotonicity comes from — the physics is monotone, the abstraction is not

The derivative of cell_fall in slew across the load columns runs −15.0, −6.2, +15.0, +53.5, +118.5, +226.9, +335.5 ps (measured, slew step 0.65→1.5 ns) — a smooth zero crossing between 1.3 and 3.6 fF, i.e. two competing deterministic terms, not noise. The mechanism: delay is anchored at the input's 50% crossing, but the NMOS conducts from V_th ≈ 25–30% VDD, so a slow ramp gives the output a head start proportional to slew; at light load the discharge is nearly instantaneous and the head start wins (delay decreases, eventually going negative — real Liberty tables contain negative delays); at heavier load the slew-degraded discharge time dominates and the usual sign returns.

At the waveform level there is a genuine monotonicity theorem by scalar ODE comparison: with C·dV/dt = −I(V_in(t),V) and I increasing in V_in (a property E1's interval model must state), pointwise-ordered input waveforms give pointwise-ordered outputs, hence monotone crossing times for every threshold. The non-monotonicity is manufactured by the quotient to (t₅₀, slew): raising slew with the anchor fixed moves the waveform earlier below the anchor and later above it — the two ramps are incomparable in the pointwise order, light loads read the below-anchor part, heavy loads the above-anchor part. The abstraction fails to respect the order the physics preserves.

Consequently a faithful recomputation (L0/07's DAE enclosure) will and must reproduce the non-monotonicity — it is a property of the defined quantity, not of simulation noise — and the repair is one of:

1. Enclosure over the quotient (current plan): four-corner interpolation, slew intervals in 08. Sound, mildly pessimistic, no new theory.
2. Per-arc sign certificates from the library census; interval fallback only on flagged cells. The smooth zero crossing suggests the flagged region is small and characterisable.
3. Waveform-envelope STA: propagate earliest/latest waveform bounds instead of (arrival, slew) scalars — monotone by the comparison lemma at every composition step, with the scalar tables as a lossy abstraction. Industry's CCS/ECSM models are a gesture in this direction; for a verified engine it is arguably the principled foundation, and it dissolves the timing half of M4, leaving only the genuine P/V/T-parameter monotonicity question.

The correlation structure

The parameter space is not one box. A sound model distinguishes three tiers, because they compose differently:

Getting these tiers wrong in either direction is the classic failure: linear accumulation of local variation makes deep paths unclosable (the √n is what rescues them — the same nothing-accumulates pattern as everywhere else in the stack); ignoring shared clock prefixes double-charges skew and fails hold checks that actually pass.

The formal object: Θ = Θ_global × Πcells Θ_local, delay arcs as functions on Θ, and P4 as the axiom "the fabricated die's parameters lie in Θ" — which absorbs what E4's empirical half used to say. The soundness theorem quantifies over Θ and the corner check plus quadrature bound plus CPPR must jointly dominate it.

Derates, honestly

Industrial OCV derates (flat ±% margins) are an engineering approximation of the quadrature bound — a linearisation applied uniformly. In a verified setting they are either derived (from the local-σ data, D3/D4) or replaced by the quadrature computation itself. Advanced-node POCV/statistical timing is this file's content done properly by industry — at 130 nm the simpler tiered model suffices, which is one more way the node choice keeps L1 tractable.

Obligations

1. The vertex theorem with per-arc monotonicity certificates, and the measured fallback set.
2. The three-tier composition theorem: corner ∘ quadrature ∘ CPPR dominates Θ.
3. The seam with 08: slew merging interacts with tier 2 (merged slews across differently-derated paths), which is where graph-based analysis quietly loses soundness.

First experiments

• The library-wide monotonicity census (shared with 08) — it decides how big the fallback set is, i.e. whether M4 is a footnote or a project.
• Compute one real path's slack three ways — flat derate, quadrature, full interval — and compare the pessimism. This is the number that tells you what soundness costs at this node.

Effort

Months, gated on the census. The mathematics is elementary; the work is stating the tier model so that P4's axiom content is exactly the empirical residue and nothing more.

L1/10 — The clock: generation and distribution

Background

Everything in this layer is measured against clock edges, so something must make them. On many chips the making is on-die and analog — a ring oscillator disciplined by a PLL — which drags a deliberately non-synchronous circuit into the netlist and forces an excision-and-contract treatment. This design keeps the analog problem off the die: the core clock arrives at a pad, generated by the board (a crystal oscillator module or an FPGA host), and the chip only distributes it. The generation contract still exists — edges must keep coming, within a stated period interval, with bounded jitter — but it moves wholesale into the environment's promises (P6's family, a board-level X4-class datasheet claim), where a purchased oscillator module's numbers are exactly the evidence the contract wants. What remains on-die is the distribution problem, plus one new participant most flat designs lack: clock gates.

The jitter physics is worth keeping in view even with generation off-die: an oscillator has no sense of absolute time. Amplitude disturbances die out, but a disturbance along the cycle — arriving a femtosecond early stays a femtosecond early forever — is never corrected, so thermal noise accumulates in the phase as a random walk. The model downstream is built to be immune to this (it indexes by edge number and constrains only edge-to-edge intervals, so the divergent absolute phase never appears in any hypothesis), and the residue appears wherever the chip must agree about time with the outside world — the UART's baud budget, chiefly.

The distribution side has its own vocabulary. The clock reaches thousands of flops through a clock tree of buffers, built by a synthesis step called CTS (clock tree synthesis); insertion delay is the source-to-flop travel time through the tree, and skew is the difference in insertion delay between two flops — the quantity the hold check consumes, since a race between two flops is run against their relative edge timing. The trap this chapter defuses: it is tempting to file the clock tree under "plumbing that preserves function," and it is not — modern flows deliberately unbalance the tree ("useful skew") and insert thousands of pure delay buffers to fix hold; the tree is a load-bearing participant in correctness, and the arrival function it realises is a first-class object of the proof.

Statement

Produce the clock arrival function arr : Flop → interval that 03 presupposes, with the generation contract imported from the environment and the gating conditions made explicit.

Generation — imported, not excised

The clock source contract, stated at the pad:

1. Frequency: consecutive rising edges are separated by a period in a stated interval — the board oscillator's datasheet promise (X4-class), plus the pad and receiver path's contribution.
2. Jitter: cycle-to-cycle deviation bounded, accumulated phase unconstrained — consumed only by L5's absolute-time interfaces (the UART budget; the start-bit resync re-anchors each frame).

No on-die oscillator means no excision, no limit-cycle proof on the critical path, and no software-reachable frequency knob — the sharpest configuration threat most chips carry is absent by construction (L5/05). The clock_tap output pad closes a loop most chips leave open: the internal clock is observable, so the generation contract is bench-checkable against the die itself.

Distribution

The clock network is CTS output: buffers, inverters, delay buffers for hold repair (the flow inserts thousands — the measured census lands in findings when the flow's layout is final), and — new relative to a flat design — integrated clock-gate cells, one per generated gating domain, driven by the RTL's gating wrappers (L3/02's primitive).

Cleanliness. Every flop's clock pin is reachable from a clock source through clock-cell types only, with no data-dependent logic except declared gating. A mechanical reachability check on the netlist, and the licence for L2's deletion of the entire network into the sentence "all flops whose gate is enabled update together." The check enumerates the gating cells rather than assuming them absent, because they are present by design here: each adds a conditional-arrival term and an enable-stability check — the gate's enable must be stable across the clock's high phase, which is precisely what the ICG's internal latch guarantees if the latch's own timing is met; the obligation composes the cell-level contract with tree-level arrival.

Arrival enclosure. STA over the clock network's own arcs yields per-flop insertion delay intervals; arr(f) is that interval widened by the imported jitter bound. Skew — the difference between two flops' arrivals — is what the hold inequality consumes, and CPPR (09) exists precisely because launch and capture share a tree prefix whose variation cancels.

CTS is not logically neutral. This deserves its own emphasis because the L1-era intuition "place-and-route preserves function" fails here: hold correctness depends on skew, useful-skew methodology deliberately unbalances the tree, and this flow's hold repair inserts delay buffers by the thousand — cells that exist purely to shape arr.

What arr's width is made of

arr(f) = nominal insertion delay
         ± tree variation (corner + OCV tiers, 03)
         ± imported source jitter (the pad contract, above)
         ± duty/pulse-width effects for the flop's min-pulse checks
         (+ the gating condition, for flops behind a clock gate)

Recovery/removal checks on asynchronous set/reset pins, and minimum-pulse-width checks, are the same window rule as setup/hold with different table entries — they ride along in 08 once arr is available; no new theory.

Ordinal time, and where the period claim actually lands

03 indexes the semantics by the realised edge sequence, so phase diffusion is quotiented out and the per-interval deviation T_n − T_nom splits three ways with three fates:

1. Stochastic period jitter: picoseconds against a 50 ns period — a Gaussian-tail term, discharged P3-style, not carried.
2. Accumulated jitter over bounded horizons: enters only L5's absolute-time interface claims (the UART frame budget — negligible; the start-bit resync re-anchors each frame).
3. Deterministic period offset: the SDC's create_clock -period is a claim about the board's oscillator that nothing on the die enforces. Closure is valid only if the delivered period ≥ the signoff period — an environment condition (P6/V-family), stated in L5's operating conditions as the board's obligation, not a software-reachability question, because no on-die register can change the frequency.

Obligations

1. The cleanliness check as a tool run against the hardened netlist, including the gating-cell census and per-gate enable-stability obligations.
2. arr as a derived object: clock-network STA + imported jitter, with the CPPR-relevant tree structure preserved rather than flattened.
3. The pad-clock contract statement — period interval + jitter bound — as the formal import boundary, with the board oscillator's datasheet as its X4 evidence.
4. The secondary clock pins (jtag_TCK, the serial link clock) each get the same treatment at lower stakes — their domains' trees, gates, and contracts (04's completeness table).

First experiments

• Run the cleanliness reachability check; count and locate the gating cells. Cheap, and it converts "clock network clean" from assumption to measurement — the same upgrade W1–W4 made for well-formedness.
• Extract per-flop insertion delays from the flow's timing reports and plot the skew distribution — the shape of the hold-repair problem made visible.

Effort

The checks: weeks. The gating obligations are the one genuinely new piece relative to a flat ungated design, and they are cell-contract compositions, not new theory.

L1/11 — Boundaries: the window hypothesis at the edge

Background

The setup/hold guarantee rests on a shared clock: every flop's input settles in time because the launching flop was tripped by a related edge one period earlier. A signal arriving from outside — a button press, a byte from a device on its own oscillator — has no such relationship. It changes whenever it changes, which will sooner or later be exactly inside some flop's forbidden window. This is the clock-domain crossing (CDC) problem, and it cannot be engineered away, because it is not an engineering defect — it is a small impossibility theorem. A circuit asked to decide, in bounded time, which side of an edge an arbitrarily-timed event fell on is being asked for a discontinuous function of a continuous input; some input must land on the boundary of the decision. Physically, a flop capturing a transitioning input can be caught metastable: balanced at the unstable equilibrium between 0 and 1 — the ball on the top of the hill — its output hovering at an invalid middle voltage for an unbounded time before restoration finally tips it to a rail.

Unbounded, but not unpaid-for: the escape probability is exponential in the settling time allowed (e^{−t/τ}, with τ a few gate delays). The standard gadget exploiting this is the two-flop synchroniser: the first flop takes the hit — it is permitted to go metastable — and its output is given a full clock period to settle before the second flop samples it; the residual probability that metastability survives that long is astronomically small per event, and summed over events it becomes a quantified failure rate — the industry's MTBF (mean time between failures) calculation, and the origin of the N_sync · P_meta(T) term in the project's top-level ε. This is one of the two places in the entire tower where correctness is genuinely probabilistic rather than certain (the other is particle strikes), which is why the synchroniser gets a precise treatment below rather than a nod.

The chapter's organising idea is that "no clock relationship at all" is only the worst rung of a ladder. Interfaces come with graded degrees of timing relationship — same clock; clock travelling alongside the data (source-synchronous, how SPI works); same frequency but unknown phase (mesochronous); nominally-same frequency with drift (plesiochronous, from Greek "close in time"); nothing (asynchronous) — and each rung supports a cheaper gadget, with a weaker assumption about the world, at a lower price. (The mid-ladder gadgets are FIFOs — first-in-first-out buffer queues that absorb phase or rate mismatch at a cost in latency.) Placing each of the chip's real interfaces on its correct rung, and paying each rung's exact price and no more, is the discipline this chapter enforces.

Statement

The bridge theorem's input-stability hypothesis is stated against the CPU's clock, and the world is not on that clock. The hypothesis is never projected outward — it is weakened at the boundary and re-manufactured inside: every interface has a gadget that accepts a strictly weaker assumption about the world and produces signals satisfying the window hypothesis internally, at a price.

This file owns the multi-domain composition of 07 and the P1 accounting.

The ladder

What can be assumed depends on how much clock relationship exists. Each grade has its gadget, its residual external assumption, and its price:

Reading down: the assumption weakens phase → transported phase → frequency → tolerance → rate, and the price climbs latency → throughput → probability. Note that "same nominal frequency from a different oscillator" is not synchronous — independent oscillators drift unboundedly in phase; only clocks derived from one source give windows.

This is the restoration pattern's third instance. Gates restore levels, clock edges restore time, boundary gadgets restore phase: the invariant is re-established at the boundary instead of the error propagating. It is why the window hypothesis never has to leave the die.

The synchroniser, precisely

The bottom rung deserves its formal statement because it is where determinism ends:

First flop: deliberately exempted from the window hypothesis; on violation its output is unconstrained (03's escape hatch) but restoration drives it to a rail with P(unresolved after t) ≈ (T₀/T_c)·e^{−t/τ}, τ the metastable saddle's unstable eigenvalue (M8, an enclosure modulo E1). Second flop: its window hypothesis is established by ordinary STA on the flop-to-flop path — a full period of settling.

No assumption about the input's phase survives. The irreducible external assumptions are rate: pulses shorter than a period can be missed outright, and the arrival statistics enter the MTBF. Both are P6-class environment facts, which is exactly where P1's residue was already filed. N_sync · P_meta(T) in the overview's ε is the sum of these per-boundary terms.

Per-frame clock recovery (UART RX) is a hybrid rung: synchronise once on the start edge (paying P1 once per frame), then rely on frequency tolerance — ±2–3% over ~10 bit periods — rather than phase. This is where P6's clock-accuracy bound does quantitative work.

Multi-domain composition

The per-domain bridge theorem composes across declared boundaries:

Partition the flops by clock domain. If each domain satisfies 07's hypotheses internally, and every inter-domain net crosses through a ladder gadget whose external assumption holds, then the composite implements a network of Mealy machines communicating through nondeterministic-latency channels — with the channel nondeterminism bounded by the gadget contracts, and ε summing the P1 terms.

The abstraction above L1 is therefore not one Mealy machine but this network; for this design it collapses back to nearly one machine because the secondary domains (the JTAG port's TCK domain and the serial link's clock domain) are low-speed control and transport paths, each meeting the core through generated synchroniser structures.

The outward direction

Symmetric, and easy to forget: the world's flops need our outputs stable in their windows. For each interface the proof exports a guarantee in the same graded vocabulary — a derived AC-timing table (clk-to-out min/max from STA) for synchronous peers, a frequency-accuracy bound for the UART TX, minimum pulse widths for async consumers. B3's composition at L5 is precisely matching our exports against the peers' assumptions and vice versa. The datasheet AC-timing page is the theorem-shaped version of this, derived rather than characterised.

The boundary inventory

A structural gift of the generated design: the crossings are library instances — the framework's async queues and reset synchronisers, named as such in the emitted RTL — so the inventory is an enumeration of known module types rather than a hunt for hand-rolled patterns, and the synchroniser predicate checks instances of three shapes instead of arbitrary flop pairs.

Obligations

1. The synchroniser predicate (structural: two-flop chain, no fanout from the first flop, one domain) — shared with 04's asynchronous class.
2. The multi-domain composition theorem above.
3. The per-boundary P1 ledger: enumerate every crossing (this list is P1's scope) and its N_sync contribution.
4. The exported AC-timing table as a derived artifact, handed to L5.

First experiments

• Enumerate every inter-domain net and every async input; check each lands on one of the framework's synchroniser shapes. This is simultaneously 04's completeness discharge and the P1 ledger's seed — one experiment, two deliverables.
• Compute the UART tolerance budget from the configured divisor and check it against the board oscillator's spec (P6/X4).

Effort

Weeks for the inventory and predicate; the composition theorem is months and leans on 07's form.

L1/12 — The geometric checks

Background

This chapter collects the layer's finite, mechanical checks, and three of them guard against physical phenomena that have not yet been introduced. Each is a classic chip-killer with a geometric cure.

Latch-up is CMOS's oldest self-destruct mode. The wells and diffusions that form a chip's transistor pairs also, unavoidably, form a parasitic four-layer PNPN structure — a thyristor, a device whose defining property is that once triggered it conducts hugely and latches on, held by its own feedback until power is removed. Triggered (by a voltage transient or a particle strike), the parasitic thyristor shorts the supply rails through the silicon, and the chip either browns out or cooks. The cure is well taps: frequent, low-resistance connections tying each well solidly to its supply rail, which starve the parasitic structure of the voltage drop it needs to trigger. "A tap within distance d of every device" is the design rule; the deeper reading — developed in L0 — is that tap coverage removes a second solution branch of the device equations, making the transistor's nominal behaviour the only one available.

Multi-cell upsets concern memory protected by ECC (error-correcting codes — extra check bits stored alongside each data word, enough to correct any single flipped bit). The code's mathematics assumes at most one bit of a word fails at a time; but a single particle strike ionises a region, and can flip several physically adjacent cells at once. The cure is interleaving: place the bits of one logical word physically far apart, so one strike's radius covers at most one bit per word. Note what kind of fact this is — a coding-theory assumption discharged by placement geometry, checkable in neither the netlist (which has no positions) nor the code's algebra (which has no particles), only in the layout.

The antenna effect is the strangest of the three: a defect mechanism of the unfinished chip. During fabrication, plasma etching deposits electric charge on whatever metal is exposed; a long wire connected, at that mid-fabrication moment, only to a transistor gate funnels all its collected charge into the gate's few nanometres of oxide and punctures it — destroying the transistor before the chip is even complete. Whether this happens depends on the order layers are built: the wire's eventual connection to a protective diode may not exist yet when the charge arrives. Hence the oddity flagged below: the antenna check quantifies over prefixes of the build sequence — it is a property of the fabrication history, not of the finished geometry, and the finished layout alone cannot express it.

Statement

The finite, decidable obligations L1 owns. These are the discharge points for conditions other layers only state — see L0/06's dispatch table. All are near-linear; none needs a PDE. They are gated on extraction and on having placement data, not on difficulty.

The checks

G1 — tap coverage (discharges V5)

∀ device d.  ∃ well tap t.  dist(d, t) ≤ d_max   (same well)

Nearest-neighbour query over device and tap positions; O(n log n) with a k-d tree. A finished layout carries tap cells by the tens of thousands (the flow places them on a fixed grid), so the tap set is large and the query is the whole cost.

This is a hypothesis of well-posedness, not a reliability rule. Latch-up is a second solution branch of the stationary device PDE (M1); tap coverage destroys the parasitic thyristor and hence the branch. Filing it under reliability is the field's convention; it is what makes "the transistor's I-V characteristic" well-defined at all.

G2 — ECC bit interleaving (discharges X2)

∀ ECC word w.  ∀ bits b ≠ b' ∈ w.  dist(cell(b), cell(b')) > R_MCU

where R_MCU is the measured multi-cell-upset radius — a D3/D4-class empirical input, not something derivable.

The sharpest cross-layer obligation in the project. ECC's independence assumption is discharged by layout geometry: the netlist cannot see placement, the code's algebra cannot see particles, and the obligation lives in the GDS where neither can look. Needs the ECC word structure as an input, which comes from L3/L5, so it is the one check here that is not self-contained.

Applicable only if the design has ECC — the SRAM macros and the tile configuration should be examined before assuming so (the tiny configuration elides ECC).

G3 — antenna ratio

∀ net n. ∀ layer ℓ. ∀ prefix P of the process order.
    area(metal(n) ∩ P) / area(gate(n) ∩ P)  ≤  ratio_max
    ∨  ∃ protection diode connected to n within P

The odd one out: it quantifies over prefixes of the build sequence, not over the finished layout. Charge accumulated on floating metal damages a gate oxide during processing, and only until the protecting diode's layer is deposited. So the finished layout carries no record of whether the check passes — the process order is an input.

It is why this design carries 44,541 antenna diodes (diode_2), and it is the clearest case in L1 of a rule that cannot be phrased as a property of M alone.

G4 — min width, spacing, enclosure

Exactly hypotheses (H1), (H2) of 01 and (D1)–(D3) of 02. Polygon morphology plus connected components; near-linear with a scanline.

Recall the sharpening: min-spacing ⟺ (H2), but min-width is necessary and not sufficient for (H1) — the notch and neck rules supply the rest, because erosion of a connected set can disconnect at a neck.

G5 — shielding coverage (the design-side hypothesis of M2)

∀ net pairs (n,m) beyond the truncation radius.
    grid metal is interposed, with aperture parameter ≤ a and pitch ≤ p

The combinatorial half of 10: the analysis supplies α(a/p), this check supplies that the geometry really provides the barriers the cascade assumes. Sparsely-gridded regions would fail it locally, and nobody currently looks.

G6 — fill is tied, not floating

∀ metal fill shape f.  f is connected to a rail

Floating conductors relay rather than screen — they couple in and out, shortcutting 04's aperture chain. So this is a precondition of the locality argument, not a manufacturing nicety. Trivial to check; potentially expensive to fix if it fails.

Summary

Two of the six need inputs from outside L1, and both of those inputs are things a layout tool does not record: the ECC word structure and the process order. Worth noting because it is the same pattern as the antenna rule generally — some geometric obligations are not properties of the geometry.

First experiments

• G6 on the flow's layout: is the metal fill tied? A single connectivity query, and the answer determines whether 04's argument needs its harder version.
• G1 on the extracted device positions, once L1/02's extraction runs.
• Establish whether the design has ECC at all before investing in G2.

Effort

Weeks each, gated on extraction and placement parsing rather than on the algorithms. This is the cheapest part of L1 and a reasonable place to start building infrastructure the rest of the layer needs anyway.

L1/13 — The combinatorial droop check

Edge: this file is the theorem the node carries — the combinatorial check (M-matrix monotonicity + lattice Green's function) that discharges 05's power-grid droop budget as an "N-apart"-style layout computation, the digital-crossing edge.

Making the droop check combinatorial: two collapses

The equipotential bound in 05 states what must hold; this section is how it becomes checkable without a full-chip network solve. Verifying "the supply at every cell stays within ΔV_grid under the worst workload" looks like two intractable searches — over all input workloads, and over all ~200k grid nodes. Both collapse, one to physics, one to the lattice, and what remains is combinatorial.

The current bound is structural, not statistical. The residual was written in 05 as "droop under worst-case simultaneous switching," and the honest worry is that a statistical activity estimate is unsound: logic is correlated, and an adversary (a power virus) can drive far more coincident switching than any average. The escape is to bound switching by circuit structure rather than activity. Per clock cycle each flop transitions at most once — and this bound is reachable, since a data pattern toggling every flop on one edge is a legal input, so for the sequential contribution it is not even pessimistic. Each combinational node transitions at most g times, g a structural glitch bound (distinct input arrival times ≤ logic depth). The per-cycle charge is then additive and workload-independent:

Q_cell ≤ Σ_nodes  (transitions · C_node · V) ,   transitions_flop = 1 ,   transitions_comb ≤ g

with the C_node the same L1 parasitics timing already uses. No activity model appears.

Collapse 1 — monotonicity removes the workload dimension. The DC grid is G·v = i, with G the mesh Laplacian plus the pad tie-downs to VDD — a symmetric M-matrix, whose inverse is entrywise non-negative. So the drop at any node, Δv_k = Σ_j R_kj i_j with every transfer resistance R_kj ≥ 0, is monotone in every current source, and the worst case over the admissible box 0 ≤ i_j ≤ i_j^max sits at the corner: every cell at its structural maximum, simultaneously. The exponential space of correlated workloads collapses to a single current vector — and this is the formal statement that the power virus, not a statistical peak, is the object to bound. There is nothing to search.

Collapse 2 — periodicity removes the spatial dimension. Evaluating R·i^max is still a 200k-node solve, until the tap/rail lattice is used: in the bulk G is translation-invariant, so R is a convolution and Δv = 𝒢 ⊛ i^max, with 𝒢 the discrete lattice Green's function of the mesh — for a 2-D resistor mesh a closed form (transfer resistance growing like (ρ_sheet/2π)·ln d). It is computed once on the fundamental domain (one pad's catchment cell, tens of nodes) and lifted by translation — the same quotient-by-the-lattice move that reduces tap coverage to a unit cell. Because the kernel decays, the drop at a point splits into a local term (the max current in that cell's neighbourhood — the dense-datapath worst case) and a slowly varying background (total current × a smaller effective resistance), two additive sums.

The resulting certificate is O(unit cell + defects), not O(200k), and it is sound:

1. certify the grid is a periodic mesh and read its parameters — per-layer sheet resistance, via resistances, pad pitch — a finite set from the DEF + tech LEF + extraction;
2. sum the structural Q_cell per unit cell (additive, from Liberty + the switching bound above);
3. evaluate the unit-cell Green's-function bound ≤ ΔV_grid — a closed form or a tens-of-nodes solve, not a full-chip simulation;
4. enumerate defects — SRAM holes, die boundary, met4/met5 strap-pitch changes — as a finite list of special cells with edge corrections.

What this changes for P_droop. If step 3 passes under the structural (worst-case) current, the droop residual is not a probability at all — it is discharged deterministically, and P_droop leaves ε. If it fails, the honest reading is that the grid was sized for a statistical peak and the design is only conditionally safe — exactly the power-virus exposure — which is a finding, not a modelling gap. Either way the probabilistic P_droop is replaced by a sound verdict.

Two caveats, stated plainly. Monotonicity is a DC fact; it discharges static IR-drop cleanly. The transient droop (L·dI/dt from package inductance, decap ringing) is not monotone — inductance overshoots — so it needs the unit-cell RLC response and an energy/damping bound, with the shared package L entering as a single global L·dI_total/dt term and the decap density as a lattice parameter. And the whole argument is conditional on the extracted parameters being trustworthy and the periodicity being verified rather than assumed. So: DC drop is fully combinatorial; di/dt is a small per-unit-cell dynamical bound plus one global inductive term.

Obligations

1. The combinatorial droop certificate (the two-collapses section): the M-matrix monotonicity lemma (worst case = all-cells-max), the lattice Green's-function reduction (unit cell + defect list), the structural switching bound (flops ≤ 1/cycle, comb ≤ g), and the parameter extraction (sheet/via resistances, pad pitch). Together these replace the probabilistic P_droop with a sound verdict — a pass, or a power-virus finding.
2. The transient (di/dt) piece: the unit-cell RLC bound plus the global L·dI_total/dt term — the one part that is not a pure DC sum.

Effort

Months, mostly tooling over DEF/extraction data; the two lemmas here — M-matrix monotonicity and the lattice Green's function — are the theory, and both lean on the lattice machinery (L0/06) other files already need. The node's equipotential bound (05) is what this certificate discharges combinatorially.

L0 — Physics: the device, the field, and ε

Node — the field/material, where ε lives: Field(A), the trajectory space of the transient field problem (00), the device models (02), and the error model (03); the analog, probabilistic bottom of the tower. Edge up — the electrical abstraction (the ε-crossing): within the envelope, field simulation over the cell and interconnect geometry establishes Contracts(N)'s transfer functions — carried by per-cell enclosures (07), lumping/composition (08), the interconnect capacitance enclosures (09), and screening (10) — and ε is bounded within L0's budgets, modulo E1.

Background

The bottom. Below the netlist there are no bits — only charge, fields, and dopant atoms — and this layer manufactures the digital abstraction out of that material: per-cell contracts certifying that each standard cell computes its Boolean function, within noise margins and delay intervals, under stated operating conditions. The route runs through the governing PDE's well-posedness (00), the reduction from Maxwell's equations to circuit theory (01, 08), the fitted device models carrying the project's deepest empirical axiom (02), validated per-cell numerics (07), the regime decomposition that is the digital abstraction stated as a theorem (06), the error model deciding what survives as probability (03), the envelope outside which none of it holds (04), what the whole tower bottoms out on (05), and the transistor-level cut discipline (06). This is the crunchiest material in the book; the per-chapter Backgrounds assume no physics beyond curiosity.

Statement

Two things, and they are different in kind:

1. A transistor network implements its contract. For each of the ~400 standard cells: geometry → devices → interval device model → a timed assume-guarantee contract (interval Liberty arc + regime classes, 07/06), whose untimed shadow is the cell's Boolean function. Verified once per process, amortised over every design forever.
2. The error model is Poisson, not Gaussian. Continuous perturbations are suppressed below any threshold of interest and are discharged; discrete events are carried.

The L0 / L1 boundary — resolved

There is one physical problem: Maxwell plus carrier transport over the whole die. The layer split is not "L0 = devices, L1 = wires" — it is a split by abstraction target, and both layers solve instances of the same PDE.

                 ONE field problem over the die
                              │
        ┌─────────────────────┴─────────────────────┐
   L0: on cell interiors                     L1: on the complement
   nonlinear (transport)                     linear (electrostatics)
   → terminal I-V → Boolean function         → per-net RC enclosures
        └─────────────────────┬─────────────────────┘
                              │
              L0/08: the LUMPING + COMPOSITION theorem
              "you may glue these two and get a circuit"

L0 owns both instances of the field problem — well-posedness, the quasi-static reduction, device models, the per-cell enclosures, and the linear interconnect enclosures (09, 10) — and, critically, the composition theorem that licenses gluing them into a circuit (08); all of this is the electrical-abstraction edge that lifts into L1. L1 owns the drawn geometry that defines the domain (the coloured image and its extrusion) and reads the circuit back out of it (extraction/LVS).

The four-step factoring

The proof plan, in order of logical dependence (which is not document order — notably it puts the envelope before the per-component work, as a precondition):

1. Existence, circuit-independent. The transient system has global-in-time solutions for any geometry, within the model's validity — established (Gajewski–Gröger). Uniqueness is not required: every downstream claim is an enclosure quantified over all solutions, which converts stationary non-uniqueness (M1) from a blocking assumption into a reachability obligation — see 00. "Within reasonable physical bounds" means model validity, not solution bounds: the theorem is unconditional for the model; the envelope justifies the model. [00, 01]
2. Coarse invariance, near-circuit-independent. Every solution stays in a broad safe set: bounded potentials (maximum principle) and carrier densities, no runaway — a theorem within the model, since the omitted terms (impact ionisation, electrothermal coupling) are exactly where the feedback dangers live. Excluding those is 04's envelope, whose side conditions are computable but not all structural (thermal is workload-conditional). The safe set is honest-broad: it contains U, 0, 1, transitioning, metastable, and the latched states — which step 3 must show unreachable, not assume absent. [07, 00, 02]
3. Fine regime decomposition, per component. Pin regions "0" / "1" / "transitioning", with "transitioning" a family parameterised by slew — the component's behaviour is an assume-guarantee contract on trajectory classes (an interval Liberty arc with an explicit domain): guaranteed output class given input classes, load, and a bounded local disturbance budget. Established numerically with rigorous enclosures, once per library cell. The disturbance budget's discharge is nonlocal (L1's screening) and must cover Miller feedthrough through the component. [02, 03, 05]
4. Composition = combinatorics + side conditions. Components plug together by finite checking: each edge's load / slew / coupling within the contracts' domains (not vacuous — the shipped design fails these, F2). Cuts are licensed only at restoring, near-unidirectional boundaries (channel-connected components), so every bistable loop is internal to a component. Three globals do not factor through pins — supply, clock, temperature — and need their own aggregate arguments. Conclusion: the network emulates a state machine, except at Poisson fault events and unresolved synchroniser reads, which are carried as P1/P2, never proved away. [04, 06]

The overall deliverable, restated: every solution of the field problem lies within the enclosure that the lumped semantics predicts, established by component contracts + PDE bounds + an abstract composition argument.

Subcomponents

On the existence question. For the linear electrostatic problem it is classical — Lax–Milgram on H¹ with bounded measurable coefficients — and not open at all. For the device problem (drift–diffusion) existence is established but uniqueness is not known in general, and the non-uniqueness is physically real: latch-up and snapback are second solution branches. See 00 and 02. The industry's answer is to not solve the PDE at all, which relocates the question into an empirical claim about compact models.

Interfaces

Consumes: cell layouts and the material stack (L1's geometry), an interval device model (E1). Exports: per-cell timed contracts — interval Liberty arcs with explicit domains (07) — and their Boolean shadows (06); the composition licence (08, 06); a per-cycle upset rate λ and the noise margin NM (03). The timed contracts are what L1's STA composes; omitting them from this list was the seam mismatch the 2026-07 review caught.

Axioms introduced

E1 (the tower's one physical axiom) and P2 (SEU). Formerly also E2, P3 and X2 — all discharged or rerouted in the reassessment (Axioms): 07 is E2's discharge route, 03 P3's, and X2's check moved to L1's G2 with its empirical residue (the upset radius) into P2.

Effort

1–3 years — the swing is exactly the per-cell cost that 07's first experiment prices. Dominated by 07 and 08. The Boolean-function-per-cell result is the load-bearing output; the error model is smaller but needs probabilistic machinery nothing else in the project requires.

Reading

von Neumann, Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components (1956). Bryant on switch-level (MOSSIM). Melham, Higher Order Logic and Hardware Verification. Markowich, The Stationary Semiconductor Device Equations.

L0/00 — The field problem and its well-posedness

Background

At the bottom of the tower, the chip is a lump of structured matter with voltages applied to its edge, and its "behaviour" is a solution to partial differential equations — equations constraining how quantities (potential, charge density) vary jointly across space and time, the mathematical form all field physics takes. Two systems matter here. In the insulating regions between conductors, the electric potential φ obeys the classical electrostatics equation ∇·(ε∇φ) = 0 — in words: no charge accumulates anywhere in the dielectric — with the conductors pinning φ to their voltages along the boundaries. This is a boundary value problem: the equation plus boundary data determine (one hopes) the field everywhere. In the semiconductor itself, where the action is, the governing system is drift–diffusion (the van Roosbroeck system): the potential is coupled to two populations of mobile charge carriers — electrons, and holes (the absence-of-an-electron, which moves and conducts like a positive particle) — each drifting under the field and diffusing down its own concentration gradient, with the carriers' charge feeding back into the potential. Nonlinear, coupled, and the actual content of "how a transistor works" at this level of description.

Why does a proof need to begin by asking whether these equations have solutions — a question no physicist or engineer ever asks? Because every downstream statement in this book has the form "the physical behaviour lies within this enclosure," and such a statement is about the solution. If no solution exists, the statement is vacuous; if several exist, the statement must hold for all of them or say which. Well-posedness — the standard label for existence + uniqueness + stable dependence on the data — is the property that makes "the field of this chip" a definite noun phrase. For the linear electrostatic problem this is classical mathematics with an off-the-shelf answer (the Lax–Milgram theorem, the workhorse existence result for such problems, applied to weak solutions — the integrated-against-test-functions notion of solution that modern PDE theory uses precisely because it is the one for which existence can be proved on rough geometry). For drift–diffusion the answer is genuinely incomplete — and, remarkably, the incompleteness is physical: the mathematical possibility of multiple stationary solutions corresponds to real chip failure modes (latch-up), and the design rules that prevent those failures turn out to be the missing uniqueness hypotheses. That correspondence is this chapter's payoff.

One more expectation to set. The reader may anticipate Navier–Stokes-style horror — nonlinear PDEs with famous open regularity problems, spontaneous singularities. The situation here is much kinder, for reasons the chapter makes precise: the linear problem is bounded by the maximum principle (the potential can never exceed the applied voltages anywhere — no spontaneous concentration), and drift–diffusion possesses a dissipative structure (a free energy that only decreases) that rules out finite-time blowup. The genuine dangers — avalanche breakdown, thermal runaway — are physical phenomena at the edge of the operating envelope, handled as explicit side conditions in 04, not lurking mathematical surprises.

Statement

Identify the PDE that the chip actually satisfies, and establish that it has a solution — so that "the field" in every downstream enclosure statement denotes something.

This is prior to every other document in L0 and L1. If the solution does not exist or is not unique, "the RC of net n" is not a well-defined quantity and the enclosures bound nothing.

The hierarchy of problems

From most faithful to most used:

The transient row is the one the digital abstraction actually needs. Electrons flow; the circuit is a dynamical system, not a sequence of static solutions. The stationary rows characterise the invariant sets; the transient row is what makes "you stay in the regime and move according to the abstraction" a statement at all. See 06, which is built on it.

The transient system is elliptic–parabolic — Poisson as an algebraic constraint coupled to two parabolic transport equations, so a PDAE rather than a PDE. Global existence is established, and the proof route is worth knowing about: the system carries a free-energy functional that decreases along trajectories, which is exactly the Lyapunov structure the regime-decomposition argument needs. It decreases toward thermal equilibrium, though, so adapting it to a boundary-driven steady state is the open piece.

Each row is an abstraction of the one above with an error that ought to be bounded. L0/01 handles row 1→2, this document handles row 2 and row 3, L0/02 handles the device side of row 2, and L0/08 handles row 3→4.

The top row is already a model. Drift–diffusion is not first principles: it is the diffusion limit of semiclassical Boltzmann transport, which in turn coarse-grains quantum transport — the hierarchy continues upward through energy-transport and hydrodynamic models (Markowich–Ringhofer–Schmeiser; Jüngel). The upward error terms are asymptotic, not bounded. At 130 nm drift–diffusion sits comfortably inside its validity window — channel lengths well above the carrier mean free path, quasi-ballistic corrections negligible — but that is an empirical adequacy claim about the node, and it should be recorded as part of E1's content: E1 asserts both "the fit matches the device" and, implicitly, "the PDE the fit dodges would itself have been adequate." There is no row you can point to and say this one is physics all the way down; there is only a row whose error is negligible for the question asked. 05 works out where the tower actually bottoms out and why E1 is the right place to cut it.

Row 3: the interconnect problem is settled

For ∇·(ε∇φ) = 0 with Dirichlet conditions on conductors, take the bilinear form

a(u,v) = ∫ ε ∇u · ∇v

If 0 < ε_min ≤ ε ≤ ε_max (bounded measurable — dielectric jumps are fine), then a is bounded and, by Poincaré–Friedrichs, coercive on the subspace of H¹ vanishing on the Dirichlet part of the boundary — which requires that part to have positive measure, true here since the rails are everywhere. Lax–Milgram gives existence and uniqueness of the weak solution. Equivalently by the direct method: the Dirichlet energy is coercive and weakly lower semicontinuous so a minimiser exists, and strict convexity gives uniqueness — which is also exactly the variational characterisation L1 uses for its two-sided capacitance bounds.

So this is not an open problem. It is classical, and the work is formalisation, not mathematics.

What does bite is regularity, not existence:

• Bounded measurable coefficients give only De Giorgi–Nash–Moser Hölder continuity. Higher regularity needs smoother coefficients, which dielectric interfaces do not provide. The sharp results for piecewise-constant ε are the transmission-problem estimates going back to Kellogg (1974).
• Reentrant corners: ∇φ blows up. Charge density diverges like r^(−1/3) at a right-angle conducting corner — precisely where the capacitance concentrates.
• Mixed boundary conditions (Dirichlet on conductors, Neumann on symmetry planes) are worse at corners than either alone. The right regularity framework here is Gröger's W^{1,p} theory for mixed problems on nonsmooth domains (1989).
• Unbounded domain: the die is finite but the field is not. Needs a decay condition at infinity, or a truncation with a bound — which is L1's screening argument again, from the other side.

The weak solution exists in H¹ on Lipschitz domains regardless. But numerics converge at degraded rates near singularities, so verified quadrature must handle integrable singularities of known exponent. Since the exponents are analytically known, graded meshes work; it is engineering, not research. The relevant machinery exists in pieces: Arb-style ball arithmetic for rigorous quadrature (Johansson), and — more to the point for enclosures — guaranteed a posteriori FEM error bounds with fully computable constants via equilibrated flux reconstruction (Ern–Vohralík). The latter is the natural route to "the true field is within δ of this computed one" as a machine-checkable statement rather than an asymptotic convergence rate.

Row 2: the device problem is genuinely open

The van Roosbroeck system — Poisson coupled to continuity equations for electrons and holes with Einstein relations — is nonlinear elliptic/parabolic.

• Existence for the stationary system is established (Mock, Gajewski, Markowich).
• Uniqueness is known only under near-equilibrium / smallness conditions, and in general it is not known and does not hold.

The non-uniqueness is not a mathematical artifact. Latch-up and snapback are real physical second solution branches — a parasitic thyristor in the CMOS well structure has a genuinely bistable I-V characteristic. Which is why tap cells and guard rings exist: they are there to destroy the second branch, not merely to bias the wells.

So the honest statement is:

The device-level PDE does not have a uniqueness theorem, and "the transistor's I-V characteristic" is therefore not obviously well-defined from first principles. Where it fails, the failure is a real device phenomenon that designers actively engineer against.

This is the sharpest genuinely-open mathematical question in the project.

Enclosures quantify over solutions — uniqueness may be bypassable

Every downstream statement has the form "the behaviour lies within this set." Stated universally — every weak solution from the given initial data remains in the enclosure — no statement ever selects "the" solution, and stationary non-uniqueness stops being a blocking assumption. What replaces it is a reachability obligation: from the unpowered initial state, under tap coverage, show that no solution enters the latch branch's basin.

The dynamics make this the physically correct formulation anyway: the transient initial-value problem is deterministic in a way the stationary problem is not — latch-up in real silicon is a triggered event (an injection transient kicks the state across a basin boundary), not an ambiguity about which I-V curve the device "has." The bistability lives in the stationary picture; the trajectory picture sees one history per disturbance signal.

The method also fails safe: if the second basin is reachable by some weak solution, the universal enclosure is forced to include it, the per-cell contract of 07 cannot be established, and verification stops — it does not silently certify the good branch. Uniqueness for the transient problem (known in 2D, partial in 3D — Gajewski) then becomes an optimisation that tightens enclosures, not a foundation the argument stands on.

Genericity: existence does not depend on the layout being sensible

For the linear problem, Lax–Milgram does not care about the geometry. Coercivity comes from Poincaré and boundedness of ε; neither mentions the shape. So the weak solution exists for essentially any measurable die drawing, sensible or not.

What degrades with bad geometry is regularity and the constants, not existence: a thin neck gives a large resistance, a sharp corner a stronger singularity, a bad aspect ratio a worse Poincaré constant. The solution is still there.

So the honest summary is: existence is generic in the geometry; uniqueness and useful bounds are not. Which is convenient, because it means well-posedness is not something to re-establish per design — it is a once-and-for-all theorem about the class.

No blowup — and this is where the Navier–Stokes analogy breaks

Linear electrostatics cannot blow up, by the maximum principle. Solutions of divergence-form elliptic equations attain their extrema on the boundary, so

|φ(x)| ≤ max |boundary data| = Vdd

everywhere, always. There is no mechanism for spontaneous energy concentration: superposition holds, and focusing requires either nonlinearity or wave propagation. Quasi-static (01) has removed the waves, and the equation has no nonlinearity. The field is bounded by the applied voltages, full stop.

The only singularities are geometric — r^(−1/3) field crowding at reentrant conductor corners. These are static, integrable, analytically characterised, and engineered against (they matter for oxide breakdown and electromigration). They are not spontaneous and they are not blowup.

Drift–diffusion has global existence, so no finite-time blowup there either. The reason is structural and better than the Navier–Stokes situation: the free energy is a genuine Lyapunov functional, and the dissipative structure gives a priori bounds strong enough to continue solutions globally. Navier–Stokes lacks exactly this — its energy does not control enough to prevent vortex-stretching concentration.

So there is no analogue here of the NS regularity problem. The nonlinearity is dissipative rather than energy-concentrating.

The two genuine runaway mechanisms are physical, not mathematical, and both are engineered against rather than proved away — see 04:

• Avalanche / impact ionisation. High field → carriers gain energy → create pairs → more current. Real positive feedback, and adding impact-ionisation terms is precisely what can destroy the global existence results above.
• Thermal runaway. Dissipation heats the die; leakage rises with temperature; more leakage means more dissipation. Real, and it destroys real chips (second breakdown).

Neither is spontaneous: both require the operating point to leave a design envelope, which is why they become side conditions rather than open problems.

How the industry dodges it

By not solving the PDE. Compact models (BSIM, PSP) are fitted algebraic relations between terminal voltages and currents — hundreds of parameters calibrated against measured silicon. The existence/uniqueness question never arises because no PDE is solved.

That relocates rather than removes the problem: it becomes the empirical claim E1, "the compact model adequately describes the device," which is unfalsifiable in principle and validated by measurement in practice.

Two consequences worth stating plainly:

1. A verified switch-level cell model rests on a fitted device model. L1/06's clean restoration argument bottoms out in E1. There is no first-principles route to a Boolean function that does not pass through either drift–diffusion (no uniqueness) or a fitted model (no derivation).
2. The tap-coverage rule is a hypothesis about uniqueness. "Every device within d of a tap" is what makes the single-branch assumption valid. It is normally filed as a layout rule; it is really the side condition on a well-posedness claim.

Open problems

1. Uniqueness for the stationary drift–diffusion system under operating conditions, or a characterisation of when the second branch is reachable. Genuinely open; a solution would be a contribution to semiconductor mathematics independent of this project. Note the enclosure formulation above may sidestep the uniqueness half entirely — what it needs is the reachability half: unreachability of the second basin from the unpowered state.
2. Formalise Lax–Milgram / the direct method over H¹ with bounded measurable coefficients. Settled mathematics, substantial Sobolev-space infrastructure, well beyond what current prover libraries support.
3. Rigorous treatment of the unbounded-domain truncation, shared with L1's screening bound.
4. Whether tap-coverage rules can be turned into a proved sufficient condition for single-branch operation rather than an empirical design rule.

First experiments

• Write the four-row abstraction hierarchy as formal statements with explicit error terms between rows, before attempting any of them. This alone will reveal which rows have bounds and which currently have only folklore.
• Survey what Mathlib-scale libraries actually have: weak solutions, H¹, Lax–Milgram, Poincaré. Determines whether row 3 is a year or five. The prior art to calibrate against: Boldo–Clément–Filliâtre–Mayero–Melquiond–Weis verified a full numerical wave-equation solver in Coq (method error + rounding error, end to end); Immler's HOL-ODE-Numerics in Isabelle does rigorous ODE enclosures inside the prover (used to check Tucker's Lorenz computation). Nothing comparable exists for elliptic problems, which is exactly the gap.

Effort

Statement work: weeks. The row-3 formalisation (Lax–Milgram over H¹) is Sobolev-library-scale, shared with L0/09's obligation 1 rather than owned here.

Reading

Markowich, The Stationary Semiconductor Device Equations (1986). Mock, Analysis of Mathematical Models of Semiconductor Devices (1983) — stationary existence. Gajewski & Gröger, "On the basic equations for carrier transport in semiconductors" (J. Math. Anal. Appl. 1986) — transient existence and the free-energy structure. Markowich–Ringhofer– Schmeiser, Semiconductor Equations (1990) and Jüngel, Transport Equations for Semiconductors (2009) — the model hierarchy above drift–diffusion. Grisvard, Elliptic Problems in Nonsmooth Domains — corner singularity exponents. Kellogg (1974) on interface regularity; Gröger (1989) on mixed boundary conditions. Ern & Vohralík on guaranteed a posteriori bounds. Any graduate elliptic PDE text for Lax–Milgram and De Giorgi–Nash–Moser.

L0/01 — Quasi-static reduction

Background

The full laws of electromagnetism are Maxwell's equations: four coupled field equations in which changing electric fields beget magnetic fields and vice versa, so that disturbances propagate — as waves, at the speed of light. Circuit theory knows nothing of this. When a circuit diagram says a node has "a voltage," it asserts that the whole node agrees on one value now; when Kirchhoff's current law says currents into a node sum to zero, it ignores the travel time of influence entirely. The gap between these pictures closes only because chips are small and their signals slow: if the time light needs to cross the structure is utterly negligible against the time anything meaningful changes, then every part of the field has already "caught up" at every instant, and the field configuration is just the static solution for the present boundary voltages, gliding through time. This is the quasi-static approximation, and it is the step at which "the circuit" — nodes, voltages, capacitances — comes into existence as a concept. The comparison is of feature size against wavelength (the distance a wave travels per oscillation period); at this chip's size and speed they are five orders of magnitude apart, which is as comfortable as approximations get.

Quasi-statics splits into two sub-regimes by which half of Maxwell survives. Electroquasistatics (EQS) keeps charge and capacitance and drops magnetic induction — the regime of everything L1 computes. Magnetoquasistatics (MQS) is the complementary half: current loops, inductance — the effect by which a changing current induces opposing voltage around its own loop. Inductance is the awkward one for this project's methods, for a reason worth understanding: capacitance is between nearby things (and screened — L0/10), but inductance belongs to current loops, and a loop is only closed through the signal's return path, which may run anywhere in the power grid — so there is no locality argument for it, and its extraction is a genuinely global problem. The honest treatment at this design's tens-of-MHz clock is to bound the inductive contribution and show it negligible — a checked side condition, rather than a modelling burden.

The chapter's remaining content is the shape of the error statement. Physics folklore says the quasi-static error is "second order in size-over-wavelength"; a verification needs that folklore as an inequality with a computable constant on this geometry, so it can be added to the margin budget like every other error. The mathematical form is a perturbation expansion — solve the equations as a power series in the small parameter, bound the discarded tail — and theorems of exactly this shape exist in the applied-analysis literature; what is missing is only the explicit-constant version. That gap (M6) is a fair sample of what this whole layer is: no new physics, no controversy, just the difference between "everyone knows it's fine" and a bound.

Statement

Maxwell's equations reduce to a sequence of elliptic problems, with an error bound. This is the first abstraction step and it is where "the circuit" becomes a meaningful concept at all — before it, there are only fields.

Why it is needed

Every downstream statement (RC enclosures, delay, Kirchhoff's laws) presupposes that propagation can be ignored and that charge and current are instantaneously related to potential. That is an approximation, and nobody in the flow states its error.

The content

The criterion is scale separation: feature size L ≪ λ = c/(f√ε_r).

At 130 nm in SiO₂ (ε_r ≈ 3.9), λ is roughly 1.5 m at 100 MHz and 15 mm at 10 GHz. The die is a few mm. So at this design's tens-of-MHz operating frequency the separation is five orders of magnitude and the approximation is excellent; at multi-GHz on global nets it starts to bind, which is exactly when on-chip inductance became an industry concern.

Two sub-regimes, and only one matters here:

• Electroquasistatic (EQS) — ∇×E ≈ 0, capacitance dominates. This is the interconnect regime and the one L1 solves.
• Magnetoquasistatic (MQS) — inductance, current loops. Relevant for long global nets and clock distribution at high frequency. Not local: there is no screening argument for inductance because return paths can be distant, which is why inductance extraction is much harder than capacitance extraction — the engineering response is the partial inductance formalism (Ruehli's PEEC; FastHenry is the reference extractor), which assigns loop-free per-segment values and recovers physical loop inductance only in closed sums. At this design's frequency it is negligible; that should be a stated and checked condition, not an assumption.

What the error bound should look like. Expand in the small parameter L/λ (equivalently ωL/c). The leading correction to the EQS solution is O((L/λ)²), so a rigorous statement has the form

‖φ_Maxwell − φ_EQS‖ ≤ C · (L/λ)² · ‖source‖

with C depending on the geometry. Theorems of exactly this shape exist, on the MQS side: Ammari–Buffa–Nédélec justified the eddy-current approximation of Maxwell with error bounds in powers of the small parameter (SIAM J. Appl. Math. 2000), and Raviart–Sonnendrücker did the same programme for the Darwin model (the combined EQS+MQS, radiation-free intermediate). The EQS analogue is easier and essentially folklore. What does not exist is the version this project needs: an explicit, computable C over realistic multi-material Lipschitz geometry, stated as a verification hypothesis rather than an asymptotic order. So the open problem is sharpening constants in a known theorem, not inventing the theorem.

Kirchhoff's laws are consequences of this reduction, not axioms. KCL is ∇·J = 0 integrated over a surface enclosing a node; KVL is ∇×E = 0 integrated around a loop. Both are exact in the quasi-static limit and carry the O((L/λ)²) error otherwise. This is worth stating explicitly because circuit theory is normally introduced axiomatically, and here it needs to be derived — see 08.

Status

Settled physics, standard asymptotic analysis, entirely unformalised in this context. The mathematics is a regular perturbation expansion; the work is stating it with explicit constants over realistic domains.

Open problems

1. An explicit, geometry-dependent constant in the O((L/λ)²) bound — i.e. the Ammari–Buffa–Nédélec-style result with the constants made computable. Without it the reduction is qualitative and the error cannot be folded into the margin budget.
2. A checkable side condition for when MQS may be dropped — i.e. a bound on the inductive contribution to delay, given the design's frequency and net lengths.
3. Whether the expansion is uniform near the corner singularities of 00, where ‖source‖ in the bound above is itself unbounded.

First experiments

• Compute L/λ for the actual design: die size, longest net, clock frequency, ε_r. Confirm the separation is as comfortable as it appears, and record it as a checked side condition rather than folklore.
• Estimate the inductive contribution on the longest global net and the clock spine, to justify dropping MQS.

Effort

Weeks for the statement; M6's explicit constant is the open-ended part.

Reading

Haus & Melcher, Electromagnetic Fields and Energy — the standard careful treatment of the EQS/MQS split. Ammari, Buffa & Nédélec, "A justification of eddy currents model for the Maxwell equations" (SIAM J. Appl. Math. 2000). Raviart & Sonnendrücker on the Darwin model. Alonso Rodríguez & Valli, Eddy Current Approximation of Maxwell Equations — book-length treatment of the MQS side. Ruehli on PEEC / partial inductance; Kamon–Tsuk–White (FastHenry) for what inductance extraction actually computes. Any asymptotic-analysis text for the regular perturbation structure.

L0/02 — Device models: the nonlinear part

Background

The MOSFET — the transistor of which this chip contains tens of millions — is, to first approximation, a voltage-controlled switch: voltage on the gate terminal creates or removes a thin conducting channel in the silicon between the source and drain terminals. Below a threshold voltage, (almost) no channel and (almost) no current; above it, a conducting path whose strength grows with gate drive. CMOS logic wires these switches in complementary pairs — for every input combination, either a path to the high rail or a path to the low rail, never both — so a gate's output is always actively driven to one rail.

The property that makes digital computation possible is gain: in its transition region, a small change in a MOSFET's input produces a larger change in its output. Gain greater than one is what lets each gate clean up its input — an input at 90% of the rail voltage produces an output at 99.9% — making the rail values attracting fixed points of the gate dynamics. This is the restoration that every layer above has been invoking: noise does not accumulate through a million-gate chain, because each stage snaps its signal back toward the rails. The interconnect, being linear, could never do this; all restoration in the machine comes from the devices, which is why this file calls them "the reason the digital abstraction exists" and why their model bears more epistemic weight than their share of the delay numbers would suggest.

How is the device's current-voltage behaviour actually known? Not by solving the drift–diffusion PDE — the chapter walks through why that route is barred (no uniqueness theorem, hopeless cost). Industry's answer is the compact model: a large fitted formula — BSIM4, the standard used by this process, has hundreds of parameters — calibrated against measured silicon until it reproduces the terminal currents across the operating range. It is an excellent description and in no sense a derivation, and the assumption "the fitted model faithfully describes the physical device" is the project's deepest empirical axiom (E1) — the one 05 later argues is irreducible no matter how deep one digs. Above the compact model sits one more abstraction this chapter needs: the switch-level model (Bryant's MOSSIM tradition), where the transistor is just a switch with a strength and the analysis tracks which nodes get driven, fought over, or left floating — the coarse level at which "this cell computes NAND" is actually read off. The load-bearing chain is switch-level resting on compact model resting on measurement, and the chapter's job is to make each link an explicit enclosure rather than a point-value trust.

A crash course in Bayesian inference

One tool the later sections lean on deserves its own introduction, because it is what turns "a model fitted to measurements" from a hand-wave into a bounded statement: Bayesian inference, the arithmetic of updating belief with data.

The setup is always the same. There is an unknown you care about — here, the device's physical parameters θ (a doping profile, a few mobility and recombination coefficients), fixed but unmeasured. You have data D — terminal I–V and C–V curves, a SIMS trace — each reading carrying measurement noise. And you have a forward model that, given parameters, predicts what those measurements should read. Three ingredients combine:

• The prior p(θ): what is known about θ before this data — physical constraints, not guesses. Doping is positive; it varies smoothly on the scale of a Debye length; mobilities sit in a known band. The prior is where physics that isn't in the data enters.
• The likelihood p(D | θ): how probable the observed data is if θ were the truth — the forward model's prediction compared against D through the measurement-noise model (a reading many σ off nominal is exponentially unlikely). This is where the data pulls.
• The posterior p(θ | D) ∝ p(D | θ)·p(θ): belief about θ after the data, by Bayes' rule — the prior reshaped by the likelihood, sharpened wherever the data is informative, left at the prior wherever it is silent.

The normaliser (the integral of the numerator over all θ, the evidence) is what makes this a probability, and computing the posterior it defines is the whole practical difficulty: for a few parameters with conjugate structure it is a formula, but for a PDE forward model it is a high-dimensional integral, done either by sampling (MCMC — draw θ's in proportion to the posterior; cheap, but the answer carries Monte-Carlo error) or, when you need a bound rather than an estimate, by validated integration over θ-space (rigorous, expensive).

The payoff is the credible interval: for any quantity Q(θ) you actually want — a delay, an I–V at an unmeasured bias, a stress response — push the posterior through Q and read off a region that holds it with posterior probability ≥ 1 − δ ("the true delay lies in [a, b] with probability 0.999"). That is the object the reforged E1 below produces, and it is why a fitted model can say something bounded about points it never measured: the forward model carries belief from the measured points into the unmeasured ones, and the prior keeps the extrapolation honest. Two cautions travel with it, developed below — the answer depends on the prior, so it must be declared; and the likelihood silently assumes the forward model is correct, so an approximate model needs an explicit discrepancy term or its posterior will be confidently wrong. (The one place the project already needs probabilistic machinery — ECC sufficiency, 03 — is a cousin of this; the reasoning layer is shared.)

Statement

Give each transistor a terminal I-V relation valid over the operating range, as an enclosure rather than a point value, and identify what that relation rests on.

This is where the nonlinearity lives, where restoration comes from, and where the project's deepest empirical axiom sits.

Why devices are special

The interconnect is linear: superposition applies, the network has a rational transfer function, model order reduction is exact, and rigorous enclosures are available (L1).

Devices are nonlinear, and they are the reason the digital abstraction exists — gain

1 in the transition region is what makes the rails attracting fixed points. So they carry disproportionate importance relative to their contribution to the numbers (which is smaller than interconnect's at any modern node).

Three routes, and their costs

Route A — solve drift–diffusion. The van Roosbroeck system. Existence established; uniqueness not known in general and genuinely false where latch-up or snapback occur (see 00). Even setting that aside, a per-device PDE solve is computationally hopeless at 400 cells × operating range × corners.

Route B — compact models (what industry does). BSIM or PSP: fitted algebraic relations with hundreds of parameters, calibrated against measured silicon. Deterministic, fast, composable. Cost: axiom E1, unfalsifiable in principle, and it gets thicker at smaller nodes as quantum confinement, quasi-ballistic transport and self-heating are folded into the fit.

Route C — switch-level abstraction. Model the MOSFET as a bidirectional switch with strength and charge sharing (Bryant's MOSSIM lineage; Melham's HOL CMOS work). This is the target abstraction for producing Boolean functions, and it is far coarser than either of the above.

The chain actually used is C resting on B: the switch abstraction's justification is the device's I-V characteristic, which comes from a fitted model. There is no route to a Boolean function that avoids either a non-unique PDE or an underived fit.

With foundry-level control there is a fourth option worth noting: define the cell library at transistor level and prove cell → Boolean via switch-level modelling, pushing the axiom down to "the switch-level MOSFET abstraction is sound." That covers the whole library at once instead of per-cell characterisation, and is a strictly better axiom. Not available for validating someone else's shipped design.

What must actually be proved

For each cell, the obligation is not "the device model is right" but:

Given the device model as an enclosure over the operating range and corners, the cell's terminal behaviour lies within a region from which the Boolean function can be read off with positive noise margin.

Two things follow. First, the device model enters as an interval, so E1's fidelity claim is "the true I-V lies in the enclosure," which is weaker and more defensible than "the model is correct." Second, the switch-level abstraction only has to be valid coarsely — you need the ON/OFF distinction and enough gain, not accurate currents.

For the interval representation itself, plain intervals will be too loose — terminal currents share the same underlying parameters, and naive intervals count that uncertainty independently at every use. The standard remedies are affine arithmetic (de Figueiredo & Stolfi), which tracks first-order correlations, and Taylor models (Makino & Berz) for higher order; both are mature and both have validated implementations.

Route A, reconsidered — and E1 as a credible enclosure

"Three routes" filed Route A under barred, on two objections; both are softer than they look, and what remains reshapes E1 rather than forbidding it.

The uniqueness objection is already handled — one level up. 00 does not assume the device PDE has a unique solution; it quantifies every downstream claim over all solutions, converting non-uniqueness from a blocking assumption into a reachability obligation. An enclosure that holds for every solution branch does not need uniqueness. (The parasitic branch — latch-up — is then excluded not by a uniqueness theorem but by the tap-coverage side condition below.) So the first objection bites only if you demand a single trajectory; for the enclosure it is a red herring.

The data objection is dischargeable by measurement. Route A is "blocked by data" (axioms.md, D4) because the doping profiles are unpublished. But you do not need the foundry's numbers — you identify them from the fabricated die: C–V profiling for net doping versus depth, I–V families across geometries for channel doping and V_th, SIMS for the chemical profile on a sacrifice, and standard TCAD inverse calibration to fit the model's parameter fields to that data. This is the project's own per-die stance applied to the device: measure the object, don't trust the spec sheet. The data floor becomes bulk material data measured on this process — exactly where 05 already places it.

Why you would want it, not merely tolerate it. This is the argument that makes Route A worth its cost, and it is 07's own argument moved down a level. A compact model fit to measurements is a point cloud with an interpolant: it asserts values where it was characterised and whatever its basis functions invent between, and goes vacuous outside the box (finding F2). A drift–diffusion solve over identified parameters is a physically-constrained continuum: once a handful of physical fields (doping, mobility, recombination) are fixed, the model's value at an unmeasured bias, corner, or disturbance is a consequence of Poisson-plus-transport, not a choice of spline. That is a low-capacity, well-validated prior, and evaluating it everywhere is principled generalisation — the same reason 07 prefers a derived interval-Liberty with an inter-sample derivative bound over the shipped point .lib, which "asserts values at the sample points and nothing in between." Points cannot bound between samples; a model can. The project already stakes this for the cell DAE; consistency demands it for the device. And it is the only vehicle for the disturbance response the envelope now quantifies over — no measurement visits every mechanical stress (04, V9) or every injected forcing (V10), so bounding those requires a model that carries the physics into regions no probe reaches.

What actually remains is validated numerics: rigorous enclosures for the nonlinear van Roosbroeck system at device scale (harder than L1's linear elliptic enclosures, and genuinely frontier), plus a conservative interval identification of the feasible parameter set. Hard, partly open — but mathematics, not a barred door.

E1, reforged. The inverse problem is ill-posed: many parameter fields fit the same terminal data and may disagree off-sample. So the honest object is not one trajectory but a set — one physical solution per parameter field consistent with the measurements — and the enclosure is their envelope. Two ways to close it, and the second is the natural one here:

• Deterministic (interval). Take the union of DD solves over the whole measurement-consistent parameter set: a guaranteed hard enclosure, no probability, as loose as the feasible set is wide. Composes with E1 in its present "the true I–V lies in the enclosure" form.
• Bayesian (credible). Put a posterior p(θ | D) on the parameters — a physical prior times a likelihood built from the forward model and the measurement-noise model — and push it through the (validated) DD solve. Every downstream quantity gets a credible enclosure: "the true I–V lies in this interval with posterior probability ≥ 1 − δ." Tighter than the worst-case union, and — the point — it composes with a conclusion that is already probabilistic. The tower ends in obs ⊑ Sys with probability ≥ 1 − ε(T); a credible E1 stops being a hard axiom propping up a probabilistic conclusion and becomes one more term in ε (the epistemic term of 03). The silent "modulo E1" asterisks become a number.

Rigour here is more than running a sampler, and each requirement drags a hidden assumption into the open — which is the gain:

1. The prior is declared. Credible sets depend on it. State the physical prior as an explicit, tunable assumption (positivity and smoothness of the doping field, physical ranges) — an honest replacement for the brute "BSIM contains the truth" — or robustify: imprecise-prior Bayes over a set of priors gives interval-valued posteriors, and conformal calibration gives distribution-free coverage with no prior at all.
2. Model discrepancy is mandatory. Calibrate an approximate model without a discrepancy term and the posterior is overconfident (the Kennedy–O'Hagan trap): tight, wrong intervals. So 05's "DD is only regime-valid" residue reappears here as an explicit, quantified discrepancy prior — small at 130 nm, but carried, and bounding it is the honest quantitative form of "how good is drift–diffusion here."
3. The posterior is computed with validated numerics, not sampled. MCMC yields an estimate with Monte-Carlo error; a theorem needs validated posterior integration or a rigorous coverage bound (PAC-Bayes), composed with the validated forward enclosure. This is the frontier piece.

None of this eliminates the axiom; it relocates E1 to a smaller, better-structured base — the drift–diffusion regime (cheap at 130 nm, 05), the measured material closures, and a declared prior-plus-discrepancy — and turns it from a deterministic hedge into a quantified, composable, data-shrinkable contribution to ε(T). That is 05's thesis — the axiom relocates, it does not vanish — made probabilistic and honest about its size.

The uniqueness side condition

Latch-up is a second solution branch of the device PDE, and the design rule that eliminates it is tap coverage: every device within a bounded distance of a well tie.

So the layout rule normally filed under "reliability" is really the side condition making the single-branch assumption valid — i.e. a hypothesis of well-posedness, not a manufacturing constraint. It belongs in the same category as L1's min-width rules, which turned out to be hypotheses of a topology-preservation theorem.

This is worth stating as a general pattern: several DRC rules are secretly the side conditions of theorems nobody has written.

Open problems

1. Uniqueness for stationary drift–diffusion under operating bias, or a characterisation of when the parasitic branch is reachable. Genuinely open.
2. Turn tap-coverage rules into a proved sufficient condition for single-branch operation.
3. Formalise a switch-level model with strengths and charge sharing, and prove it sound with respect to an interval-valued compact model. Nobody has done this for a real library.
4. Self-heating: at advanced nodes it enters the functional path. Absent at 130 nm; record as a scope boundary.

First experiments

• Take inv_1: extract its transistor netlist (magic/netgen), attach an interval-valued device model, and derive the terminal enclosure. This is the unit that gets multiplied by 400 — measuring it decides where in its one-to-three-year range L0 lands.
• Check how coarse the device enclosure can be while still yielding positive noise margin. If the margin is large (it should be, at 1.8 V), E1's precision requirement is weak, which materially reduces what must be assumed.

Effort

The inv_1 experiment: days — and it prices the whole layer (see 07). The switch-level formalisation (route C): months.

Reading

Markowich, The Stationary Semiconductor Device Equations. Bryant, "A switch-level model and simulator for MOS digital systems" (IEEE Trans. Computers 1984) — the MOSSIM II model: strengths, charge sharing, and the ternary algebra. Melham, Higher Order Logic and Hardware Verification (1993) — transistor-level CMOS in HOL, the closest existing formalisation of Route C. The BSIM4 technical manual (Berkeley) for what E1 actually asserts — the SKY130 PDK models are BSIM4, evaluated under ngspice; Gildenblat et al. for PSP, the surface-potential alternative. de Figueiredo & Stolfi on affine arithmetic; Makino & Berz on Taylor models.

L0/03 — The error model

Background

Everything below a certain scale jiggles. Thermal noise — the random motion of charge carriers at any temperature above absolute zero — makes every node voltage a fuzzy quantity, fluctuating around its nominal value with a spread set by kT/C (Boltzmann's constant times temperature over capacitance: a couple of millivolts on a femtofarad node). Since a proof cannot pretend the fuzz away, the first question of any honest error model is: with trillions of transistors switching trillions of times, why doesn't randomness simply win? The chapter's answer turns on the shape of the Gaussian tail: the probability of a fluctuation reaching k standard deviations falls as exp(−k²/2) — quadratically in the exponent — while exposure (device count × cycle count) grows only linearly. A noise margin a hundred standard deviations wide gives a per-event failure probability around 10⁻³²⁵⁷; multiply by every transistor-cycle in the universe's lifetime and it stays, for every purpose, zero. The chapter's discipline — discharge, don't carry — is to prove such exponents once and delete the term, rather than dragging an ε through ten thousand theorems. (The escape-over-a-barrier calculation behind this is Kramers' theory, the standard treatment of noise-driven escape from a potential well.)

The deleted term must be distinguished from the two that genuinely survive, and the distinctions are the chapter's spine. Particle strikes survive because they are not thermal: a cosmic-ray neutron or an alpha particle from package contamination deposits, in one hit, a hundred thousand times the energy the noise barrier holds back — the event is drawn from a different distribution than the one the margin was built against, so no margin argument touches it. Its statistics are Poisson (the mathematics of independent random arrivals — fixed rate per area per time), its consequence is the SEU (single-event upset: a flipped bit that the circuit then processes as happily as a real one), and it enters the top-level theorem as the rate λ in ε's leading term. Clock phase drift survives for a subtler reason developed in L1/10: the oscillator's phase is the one direction in the whole system with no restoring force, so thermal noise there accumulates instead of being suppressed — not a failure probability but a growing uncertainty, carried as a jitter budget.

Against the surviving bit-flips stands ECC — error-correcting codes, the digital regime's own defence. The idea, due to Hamming: store, alongside each data word, a few extra check bits computed so that any single flipped bit leaves a distinctive fingerprint (the syndrome) identifying exactly which bit to flip back. The standard memory variant, SECDED (single-error-correct, double-error-detect), corrects one and detects two; combined with scrubbing — a background process that periodically reads, corrects, and rewrites every word, so single errors don't linger long enough to meet a partner — it converts a failure rate linear in the upset rate into one quadratic in it, with the scrub interval as a tuning knob. The mathematics splits cleanly: the code's correctness is finite algebra (among the cheapest proofs in the project), while the sufficiency bound ("with rate λ and this scrub interval, uncorrectable loss is this improbable") is the one place the whole tower needs genuinely probabilistic reasoning machinery.

Statement

Determine what survives as a probabilistic term after the digital abstraction is established, and hand it upward in a form the rest of the project can consume.

Result: exactly one failure term survives at the physical layer, and it is Poisson. One disturbance also survives — clock phase diffusion — but it enters as a budget line, not a failure probability; see below.

The central distinction

Two kinds of ε get confused, and they behave completely differently:

• Probabilistic ε — exponentially suppressed by a mechanism, multiply by scale freely, discharge and forget.
• Additive-physical ε (capacitance, IR drop, skew) — accumulate linearly, need a convergent decay argument, and the bound must be on the aggregate, not per element.

Confusing them is the most common modelling error in this area. Thermal noise is the first kind; coupling capacitance is the second (see L1/X3).

A third kind: epistemic ε

Both kinds above are aleatoric — frequencies of real random events (a thermal fluctuation, a particle arrival) that a die actually draws over its life. E1's Bayesian form (02) introduces a third, epistemic: our uncertainty about the fixed but unknown device parameters given finite characterisation. It is a different animal from either aleatoric kind and must be tracked apart:

• it is a credence, not a frequency — the doping is what it is; we are uncertain about it;
• it shrinks with more measurement (more C–V/I–V/SIMS tightens the posterior), which no aleatoric term does; and
• it is prior-dependent, so it carries its modelling assumptions on its face.

Sum it into the headline ε if you like, but keep the decomposition visible, because the knobs differ. ε_aleatoric(T) — the Poisson λ, the metastability rate — is bought down only by ECC, synchronisers, and shielding; ε_epistemic(D, prior, δ) is bought down by taking more data. Collapsing them hides which lever moves which term, and hides that the epistemic part is, in principle, driven to zero by characterisation while the aleatoric part never is.

Corners are a crude shadow of the same posterior. PVT variation is filed below as "distribution over dies → yield, caught by test" — an aleatoric spread handled by a conservative box. The principled object is hierarchical: process hyperparameters φ (epistemic, from characterisation) generating per-die draws θ (the variation), p(θ | φ)·p(φ | D). The corner box is then a conservative outer bound on that predictive posterior — which is why corner methodology works, and where a principled posterior could show it loose in some directions and tight in others. The same hierarchy separates cleanly from E7 (as-fabricated geometry), a different draw in the same model. So the tower's final 1 − ε(T) carries two genuinely distinct uncertainties — the world's randomness and our ignorance — and honesty is naming both, not blending them.

Mechanisms sorted by functional form

Thermal noise: discharge it, do not carry it

Kramers escape from a basin goes as exp(−ΔE/kT). The barrier is

ΔE/kT = ½(ΔV/v_n)²,   v_n = √(kT/C) ≈ 2 mV at C ≈ 1 fF
ΔV ≈ 0.25 V  ⟹  ΔE ≈ 7,500 kT  ⟹  P ≈ exp(−7500) ≈ 10⁻³²⁵⁷

Ten trillion transistors at 10 GHz for the age of the universe is ~10⁴⁰ opportunities. Not close — and the exponent is quadratic in the margin while the scale factor is only linear in count, so no amount of scale reaches it.

A formal model should prove the barrier exceeds N·kT and then delete the term, not carry an epsilon around. Full rail-to-rail (½C·Vdd² at 1.8 V) is ~4×10⁵ kT.

The one escape from the discharge: the oscillator's phase mode

The Kramers argument requires a restoring force — it bounds escape from a basin. There is exactly one deliberately non-restoring direction in the whole system: the phase of the clock oscillator. Time-translation symmetry of a limit cycle forces a zero Floquet exponent along it, so thermal noise projected onto phase is not suppressed at all — it accumulates as a Wiener process, variance linear in time (Demir–Mehrotra–Roychowdhury is the standard theory). Jitter is thermal noise made visible by the absence of restoration. The PLL's feedback bounds the drift relative to its reference; the per-cycle residue is Gaussian with picosecond-scale σ against a much larger timing margin, so its exceedance is discharged like every other Gaussian tail — but the σ itself is a real, surviving, derivable quantity, and it is where X5's genuinely physical content lives (see M8). The discharge above is therefore correct for every regime-holding node and would be unsound applied to the clock generator.

Why particles are different in kind

A 10 MeV neutron carries ~4×10⁸ kT against a 7,500 kT barrier — about 10⁵× the energy needed. It is not a rare fluctuation of the thermal distribution; it is an energy injection from outside the bath. So the probability is not exp(−barrier/kT) but simply (arrival rate) × (cross-section) × (fraction depositing more than Q_crit).

General lesson worth carrying to every layer: in a well-designed restoring system, the tail of the distribution you modelled is never what kills it. What kills it is events drawn from a different distribution.

Rates: JEDEC's sea-level reference is ~13 neutrons/cm²/hr above 10 MeV; historical SRAM figures are ~10⁻³–10⁻⁴ FIT/bit. At 10⁹ bits that is ~10⁶ FIT ≈ one upset per thousand hours. Observable, which is why ECC exists.

Metastability breaks the abstraction in time, not in value

Restoration guarantees the flop reaches a rail — there is no steady-state half-bit. But the time is unbounded: P(unresolved after t) ≈ (T₀/T_c)·exp(−t/τ). During the unresolved window, different downstream gates can read the same mid-rail voltage differently. The signal is not a boolean, because observers disagree.

That is strictly worse than a random bit, and it is why P1 is permanent. The mitigation is to localise it: enumerate every asynchronous input and clock-domain crossing (L1), and make the theorem explicitly conditional on resolution.

Calibration note: the ~10⁻⁴³/cycle figures assume a correctly designed synchroniser with a full period of settling. A grossly violated path has percent-level rates.

Masking is computable, not merely measurable

Not every upset becomes an error. Four derating layers, three of them derivable:

• Electrical — the induced pulse attenuates through gates (restoration working for you).
• Logical — the flipped node does not affect the output. A Boolean question about the netlist.
• Temporal — the glitch misses every setup/hold window. A timing question.
• Architectural — dead register, wrong-path instruction, predictor state. The "prove it irrelevant" category from L3.

Together these knock the raw rate down by one to two orders of magnitude (AVF commonly 10–30%). Industry measures this by fault injection. All four are in principle derivable from artifacts this project already formalises — deriving derating factors rather than measuring them is a plausible novel contribution, and it is unusually well-positioned because L2 gives the netlist, L1 the timing, and L3 the architectural irrelevance argument.

The ECC interface

What L0 hands upward is a discrete channel — occasional bit flips at Poisson times. Everything above is coding theory, which is why ECC is a digital-regime object.

Two obligations of very different character:

• Functional correctness — encoder/decoder, minimum distance over GF(2): distance 3 suffices for correct-one (Hamming 1950), but SECDED requires distance 4 (the extended Hamming code) — the extra parity bit is what makes double errors detected rather than miscorrected. A finite algebraic fact, exhaustively checkable. Among the cheapest obligations in the project.
• Sufficiency — given λ, a scrub interval, and word size, bound P(uncorrectable). A renewal/Markov argument, and the only place the project needs a probabilistic reasoning layer alongside the deterministic refinement. The model is small enough for a probabilistic model checker (PRISM, Storm) to compute the bound exactly, and the in-prover route exists too — Hölzl's Markov-chain formalisation in Isabelle, or Mathlib's probability library — so this layer is tooling choice, not research.

The payoff is structural: raw upsets give failure probability linear in λ·N·T; SECDED plus scrubbing means failure needs two errors in one word within a scrub interval, so the rate goes as (λ·T_scrub)² — quadratic, with a tunable coefficient. (Two errors is a detected-uncorrectable loss; silent miscorrection needs three. The sufficiency statement should distinguish the two, since they have different consequences upstream.) That is how the abstraction survives a real, nonzero, measurable upset rate.

X2 — the sharpest cross-layer obligation in the project

ECC's independence assumption ("errors within a word are independent") is discharged by bit interleaving in the layout — physically adjacent cells assigned to different ECC words, because one particle can upset several neighbours. Multi-cell upsets are a measured, growing fraction of events as cells shrink (Ibe et al. have tracked the scaling across nodes), so the required interleaving distance is node-dependent — the hypothesis has a number in it, not just a topology.

The netlist cannot see geometry. The code's algebra cannot see particles. The obligation lives in the GDS and is invisible to every level one would naturally formalise. It is the clearest example of a correctness argument spanning from geometry to coding theory with nothing in between able to see both ends.

Open problems

1. The probabilistic reasoning layer and its interface to deterministic refinement.
2. Deriving AVF/derating from the formalised netlist and timing model.
3. Formalising X2 — stating an interleaving property over the layout and connecting it to the code's independence hypothesis.

First experiments

• Write the four-mechanism model formally, with the thermal term explicitly discharged, and check the layering composes into a single statement of the form P(T-cycle execution refines spec) ≥ 1 − (λ·A·T·AVF + N_sync·P_meta + …).
• Check whether the design has ECC at all (the tiny configuration elides it), and if not, what the raw FIT budget is and whether it matters for the claim being made.
• Enumerate every asynchronous input and CDC in the design — this list is P1's scope, and L1 needs it anyway.

Effort

Weeks for the formal model; the probabilistic reasoning layer it needs is machinery no other layer requires.

Reading

von Neumann (1956). Hamming (1950) for the code. Mukherjee et al. (MICRO 2003) on architectural vulnerability factor. JEDEC JESD89A for the standard terrestrial flux reference. Ibe et al. on multi-cell upset scaling — the empirical content behind X2. PRISM / Storm for the renewal-model computation; Hölzl's Isabelle Markov chains for the in-prover version. Demir, Mehrotra & Roychowdhury, "Phase noise in oscillators: a unifying theory" (IEEE TCAS-I 2000) — the phase-diffusion structure behind the jitter exception.

L0/04 — The operating envelope

Background

Chips can destroy themselves, and the ways they do it are the hypotheses of this chapter, so each deserves a plain description. Avalanche breakdown: in a strong enough electric field, a charge carrier gains enough energy between collisions to knock new carriers loose on impact, which are themselves accelerated — a chain reaction (impact ionisation) that multiplies current explosively. Thermal runaway: silicon's leakage current rises steeply with temperature, and leakage dissipates power, which raises temperature — a feedback loop that, past a tipping point, cooks the die. Electromigration: a sufficiently dense electron current physically drags metal atoms along with it, so a wire carrying too much current for too long literally erodes, thinning until it opens. Latch-up was introduced in L1/12's background — the parasitic thyristor lurking in every CMOS well structure. And crowbar current: during a gate's input transition, its pull-up and pull-down transistors are both momentarily partly conducting, forming a brief rail-to-rail short — harmless when transitions are sharp, a real dissipation term when they are slow.

None of these is exotic; the reason a working chip exhibits none of them is that its design keeps the operating point inside a safe operating area — a region of voltage, temperature, current density, and slew inside which every feedback loop above is starved. Datasheets draw this region as the "absolute maximum ratings" table; this chapter's job is to state it as mathematics — the disturbance bounds under which 06's invariance claims hold — and to observe that its enforcement mechanisms are, once again, humble design rules (current-density limits, slew limits, tap spacing) that are secretly the hypotheses of boundedness theorems nobody wrote. Those five are the chip's internal self-destruction modes; two environmental axes — mechanical stress and external electromagnetic forcing — round out the same envelope, and are taken up in their own section once the internal ones are stated.

One technical idea in the chapter needs advance introduction: mollification, the smoothing of a field by averaging over a small ball. It is forced by an awkward fact: at a perfectly sharp conductor corner, the idealised electric field is mathematically infinite (a mild power-law singularity), so a naive constraint "field below breakdown threshold everywhere" is violated by every geometry containing a right angle — the constraint would be unsatisfiable while real chips sit happily unbroken. The resolution is that physical corners are atomically rounded and every physical breakdown mechanism averages over a finite volume anyway, so the honest constraint bounds the field averaged at a stated physical scale. Choosing that scale is a modelling decision with real content — too small and the constraint is unsatisfiable, too large and it is vacuous — the kind of decision a formalisation must make explicitly where engineering practice makes it tacitly.

Statement

Collect the conditions under which every bound in L0 and L1 is valid, and establish that the design and its environment stay inside them.

These are the disturbance bounds of 06's robust invariance claim. Without them (I) and (P) are unconditional statements that are simply false: every one of these mechanisms does leave the invariant set, and the design's job is to make them unreachable.

The pattern

Each entry has the same shape, and it recurs enough to be worth naming:

A real physical instability, prevented by a design rule, which is therefore secretly a hypothesis of a well-posedness or boundedness claim rather than a manufacturing constraint.

This is the third time this pattern has appeared in the project. L1's min-width and min-spacing rules are the hypotheses of a topology-preservation theorem. Tap-coverage rules are the hypothesis that kills latch-up's second solution branch. And now the whole envelope. Several DRC and design rules are the side conditions of theorems nobody has written.

The envelope