The die explorer

Everything in this book is grounded in one physical artifact: the routed layout of the target chip. This page lets you look at it — the actual metal the detailed router placed, read straight from ChipTop.def and the cell GDS, rendered as vectors you can pan, zoom, and toggle.

↗ Open the explorer full-screen

What you're looking at, and where each layer proves it

The explorer is a zoom hierarchy, and each level is the subject of a layer of this book:

  • The die — 3.59 × 2.99 mm, with the five SRAM macros (the caches) carved out as labelled boxes. The floorplan and the macro contracts are L2/02.
  • The metal layers (met1–met5) — every wire the router placed, 559,285 segments. That two nets crossing on different layers don't connect, while same-layer overlap would be a short, is exactly the no-shorts half of the routing witness; the no-opens half is that each net's routing self-connects. Both are machine-checked — all 41,287 two-pin nets connect, zero shorts — by tools/routecheck.py.
  • The vias — 554,469 of them, coloured by the layer pair they bridge (li1–met1 grey-blue, met1–met2 purple, up the stack). A via is the only place two layers connect; the grey-blue li1–met1 vias are where routing meets a cell pin — the pin geometry of L1/02.
  • The cells — split into the 67,893 logic gates and flops and the 135,134 well-taps and fill. Taps carry no logic: they tie the wells to the rails to prevent latch-up (L0/06, the tap-coverage condition). Hover any cell to see what it is.
  • The transistors — zoom past ~24 px/µm and the standard cells resolve into their real geometry: green diffusion, red poly gates (a gate crossing diffusion is a transistor), blue met1. This is the L0 device level — the bottom of the tower, where the digital abstraction meets the silicon. Every instance is one of only ~122 distinct cell layouts, drawn once and placed everywhere.

How it's built

tools/chipviz.py reads the routed DEF into a compact per-layer segment blob (gzipped uint16); tools/extract-cells.py pulls the ~122 used cell masters' polygons from the GDS with gdstk; tools/build-chipviz-html.py assembles a single self-contained page that decompresses the blobs in the browser (DecompressionStream) and draws them on a canvas with viewport culling — no rendered pixels served, resolution-independent at any zoom. It regenerates from the flow artifacts; see tools/build-book.sh.